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2 files changed

+14
-4
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2 files changed

+14
-4
lines changed

pyfpga/openflow.py

+4
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,10 @@ def _prog_custom(self):
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info = get_info(self.data.get('part', 'hx8k-ct256'))
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self.data['family'] = info['family']
3535

36+
@staticmethod
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def _get_absolute(path, ext):
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return path = Path(path).resolve().as_posix()
39+
3640

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def get_info(part):
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"""Get info about the FPGA part.

tests/test_tools.py

+10-4
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
import os
2+
13
from pathlib import Path
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from pyfpga.factory import Factory
35

@@ -41,7 +43,7 @@ def test_quartus():
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generate(tool, 'PARTNAME')
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base = f'results/{tool}/{tool}'
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assert Path(f'{base}.tcl').exists(), 'file not found'
44-
assert Path(f'{base}-prog.tcl').exists(), 'file not found'
46+
assert Path(f'{base}-prog.sh').exists(), 'file not found'
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4648

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def test_vivado():
@@ -88,11 +90,15 @@ def generate(tool, part):
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prj.make()
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prj.prog()
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#
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separator = '\\'
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#
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for path in prj.data['includes']:
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assert "\\" not in path, f'invalid path {path}'
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assert separator not in path, f'invalid path {path}'
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for category in ['files', 'constraints']:
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for path in prj.data[category]:
95-
assert "\\" not in path, f'invalid path {path}'
99+
assert separator not in path, f'invalid path {path}'
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#
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if os.name == 'nt' and tool in ['diamond', 'quartus']:
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separator = '/'
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path = prj._get_bitstream()
98-
assert "\\" not in path, f'invalid path {path}'
104+
assert separator not in path, f'invalid path {path}'

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