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mc6809.c
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/*
Copyright 2015 by Joseph Forgione
This file is part of VCC (Virtual Color Computer).
VCC (Virtual Color Computer) is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
VCC (Virtual Color Computer) is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VCC (Virtual Color Computer). If not, see <http://www.gnu.org/licenses/>.
*/
#include <windows.h>
#include <stdio.h>
#include "defines.h"
#include "mc6809.h"
#include "mc6809defs.h"
#include "tcc1014mmu.h"
#include "OpDecoder.h"
#include "Disassembler.h"
//Global variables for CPU Emulation-----------------------
#define NTEST8(r) r>0x7F;
#define NTEST16(r) r>0x7FFF;
#define OTEST8(c,a,b,r) c ^ (((a^b^r)>>7) &1);
#define OTEST16(c,a,b,r) c ^ (((a^b^r)>>15)&1);
#define ZTEST(r) !r;
typedef union
{
unsigned short Reg;
struct
{
unsigned char lsb,msb;
} B;
} cpuregister;
#define D_REG d.Reg
#define PC_REG pc.Reg
#define X_REG x.Reg
#define Y_REG y.Reg
#define U_REG u.Reg
#define S_REG s.Reg
#define A_REG d.B.msb
#define B_REG d.B.lsb
#define DP_REG dp.B.msb
static cpuregister pc,x,y,u,s,dp,d;
static unsigned int cc[8];
static unsigned char *ureg8[8];
static unsigned char ccbits;
static unsigned short *xfreg16[8];
static int CycleCounter=0;
static unsigned int SyncWaiting=0;
static unsigned int temp32;
static unsigned short temp16;
static unsigned char temp8;
static unsigned char PendingInterupts=0;
static unsigned char IRQWaiter=0;
static unsigned char Source=0,Dest=0;
static unsigned char postbyte=0;
static short unsigned postword=0;
static signed char *spostbyte=(signed char *)&postbyte;
static signed short *spostword=(signed short *)&postword;
static std::vector<unsigned short> CPUBreakpoints;
static std::vector<unsigned short> CPUTraceTriggers;
static int HaltedInsPending = 0;
//END Global variables for CPU Emulation-------------------
//Fuction Prototypes---------------------------------------
_inline unsigned short CalculateEA(unsigned char);
static void setcc (unsigned char);
static unsigned char getcc(void);
static void cpu_firq(void);
static void cpu_irq(void);
static void cpu_nmi(void);
static void Do_Opcode(int);
static void P2_Opcode(void);
static void P3_Opcode(void);
//END Fuction Prototypes-----------------------------------
void MC6809Reset(void)
{
char index;
for(index=0;index<=5;index++) //Set all register to 0 except V
*xfreg16[index] = 0;
for(index=0;index<=7;index++)
*ureg8[index]=0;
for(index=0;index<=7;index++)
cc[index]=0;
dp.Reg=0;
cc[I]=1;
cc[F]=1;
SyncWaiting=0;
pc.Reg=MemRead16(VRESET); //PC gets its reset vector
SetMapType(0);
return;
}
void MC6809Init(void)
{ //Call this first or RESET will core!
// reg pointers for TFR and EXG and LEA ops
xfreg16[0]=&D_REG;
xfreg16[1]=&X_REG;
xfreg16[2]=&Y_REG;
xfreg16[3]=&U_REG;
xfreg16[4]=&S_REG;
xfreg16[5]=&PC_REG;
ureg8[0]=(unsigned char*)&A_REG;
ureg8[1]=(unsigned char*)&B_REG;
ureg8[2]=(unsigned char*)&ccbits;
ureg8[3]=(unsigned char*)&dp.B.msb;
ureg8[4]=(unsigned char*)&dp.B.msb;
ureg8[5]=(unsigned char*)&dp.B.msb;
ureg8[6]=(unsigned char*)&dp.B.msb;
ureg8[7]=(unsigned char*)&dp.B.msb;
cc[I]=1;
cc[F]=1;
return;
}
VCC::CPUState MC6809GetState()
{
VCC::CPUState regs = { 0 };
regs.CC = getcc();
regs.DP = DP_REG;
regs.A = A_REG;
regs.B = B_REG;
regs.X = X_REG;
regs.Y = Y_REG;
regs.U = U_REG;
regs.S = S_REG;
regs.PC = PC_REG;
regs.IsNative6309 = false;
return regs;
}
void MC6809SetBreakpoints(const std::vector<unsigned short>& breakpoints)
{
CPUBreakpoints = breakpoints;
}
void MC6809SetTraceTriggers(const std::vector<unsigned short>& triggers)
{
CPUTraceTriggers = triggers;
}
// Do instructions for CycleFor cycles. Return number cycles over.
int MC6809Exec(int CycleFor)
{
static unsigned char opcode=0;
extern int JS_Ramp_Clock;
int PrevCycleCount = 0;
CycleCounter=0;
// Instruction Loop
while (CycleCounter<CycleFor) {
// CPU is halted.
if (EmuState.Debugger.IsHalted()) {
return(CycleFor - CycleCounter);
}
// CPU is stepping.
if (EmuState.Debugger.IsStepping()) {
Do_Opcode(CycleFor);
EmuState.Debugger.Halt();
return(CycleFor - CycleCounter);
}
// Halted instruction pending.
if (HaltedInsPending) {
VCC::ApplyHaltpoints(0);
Do_Opcode(CycleFor);
VCC::ApplyHaltpoints(1);
HaltedInsPending = 0;
return(CycleFor - CycleCounter);
}
// Do interrupts
if (PendingInterupts) {
if (PendingInterupts & 4)
cpu_nmi();
else if (PendingInterupts & 2)
cpu_firq();
else if (PendingInterupts & 1) {
if (IRQWaiter==0) // This is needed to fix timing problems
cpu_irq();
else
IRQWaiter-=1;
}
}
// Wait for Sync
if (SyncWaiting==1) // Note: Assert interrupt clears sync waiting
return(0);
// Any CPU Breakpoints set?
if (!EmuState.Debugger.IsStepping() && !CPUBreakpoints.empty()) {
if (find(CPUBreakpoints.begin(), CPUBreakpoints.end(), pc.Reg) != CPUBreakpoints.end())
{
EmuState.Debugger.Halt();
return(CycleFor - CycleCounter);
}
}
// Is the execution trace enabled - but currently not running?
if (EmuState.Debugger.IsTracingEnabled() && !EmuState.Debugger.IsTracing())
{
// Only Start Tracing when we hit a start trigger.
if (!CPUTraceTriggers.empty())
{
if (find(CPUTraceTriggers.begin(), CPUTraceTriggers.end(), pc.Reg) != CPUTraceTriggers.end()) {
EmuState.Debugger.TraceStart();
}
} else {
// Otherwise start right away.
EmuState.Debugger.TraceStart();
}
}
// Trace is running.
if (EmuState.Debugger.IsTracing()) {
EmuState.Debugger.TraceCaptureBefore(CycleCounter, MC6809GetState());
}
// Do an instruction
Do_Opcode(CycleFor);
// After instruction trace capture
if (EmuState.Debugger.IsTracing()) {
EmuState.Debugger.TraceCaptureAfter(CycleCounter, MC6809GetState());
}
// Advance the JoyStick Ramp timer
if (JS_Ramp_Clock < 0xFFFF) {
JS_Ramp_Clock += CycleCounter-PrevCycleCount;
}
PrevCycleCount = CycleCounter;
} // End instruction loop
return(CycleFor-CycleCounter);
} // End MC6809Exec
// Execute an instruction
void Do_Opcode(int CycleFor)
{
static unsigned char msn,lsn; //Most signifcant, least significant nibbles
switch (MemRead8(pc.Reg++)) {
case NEG_D: //0
temp16=(dp.Reg |MemRead8(pc.Reg++));
postbyte=MemRead8(temp16);
temp8=0-postbyte;
cc[C]=temp8>0;
cc[V]= (postbyte==0x80);
cc[N]= NTEST8(temp8);
cc[Z]= ZTEST(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case COM_D: //3
temp16=(dp.Reg |MemRead8(pc.Reg++));
temp8=MemRead8(temp16);
temp8=0xFF-temp8;
cc[Z]= ZTEST(temp8);
cc[N]= NTEST8(temp8);
cc[C]=1;
cc[V] = 0;
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case LSR_D: //4
temp16=(dp.Reg |MemRead8(pc.Reg++));
temp8=MemRead8(temp16);
cc[C]= temp8 & 1;
temp8= temp8 >>1;
cc[Z]= ZTEST(temp8);
cc[N]=0;
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case ROR_D: //6
temp16=(dp.Reg |MemRead8(pc.Reg++));
temp8=MemRead8(temp16);
postbyte= cc[C]<<7;
cc[C]= temp8 & 1;
temp8= (temp8 >> 1)| postbyte;
cc[Z]= ZTEST(temp8);
cc[N]= NTEST8(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case ASR_D: //7
temp16=(dp.Reg |MemRead8(pc.Reg++));
temp8=MemRead8(temp16);
cc[C]= temp8 & 1;
temp8 = (temp8 & 0x80) | (temp8 >>1);
cc[Z]= ZTEST(temp8);
cc[N]= NTEST8(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case ASL_D: //8
temp16=(dp.Reg |MemRead8(pc.Reg++));
temp8=MemRead8(temp16);
cc[C]= (temp8 & 0x80) >>7;
cc[V]= cc[C] ^ ((temp8 & 0x40) >> 6);
temp8= temp8 <<1;
cc[N]= NTEST8(temp8);
cc[Z]= ZTEST(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case ROL_D: //9
temp16=(dp.Reg |MemRead8(pc.Reg++));
temp8=MemRead8(temp16);
postbyte=cc[C];
cc[C]=(temp8 & 0x80)>>7;
cc[V]= cc[C] ^ ((temp8 & 0x40) >>6);
temp8 = (temp8<<1) | postbyte;
cc[Z]= ZTEST(temp8);
cc[N]= NTEST8(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case DEC_D: //A
temp16=(dp.Reg |MemRead8(pc.Reg++));
temp8=MemRead8(temp16)-1;
cc[Z]= ZTEST(temp8);
cc[N]= NTEST8(temp8);
cc[V]= temp8==0x7F;
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case INC_D: //C
temp16=(dp.Reg |MemRead8(pc.Reg++));
temp8=MemRead8(temp16)+1;
cc[Z]= ZTEST(temp8);
cc[V]= temp8==0x80;
cc[N]= NTEST8(temp8);
MemWrite8(temp8,temp16);
CycleCounter+=6;
break;
case TST_D: //D
temp8=MemRead8((dp.Reg |MemRead8(pc.Reg++)));
cc[Z]= ZTEST(temp8);
cc[N]= NTEST8(temp8);
cc[V] = 0;
CycleCounter+=6;
break;
case JMP_D: //E
pc.Reg= ((dp.Reg |MemRead8(pc.Reg)));
CycleCounter+=3;
break;
case CLR_D: //F
MemWrite8(0,(dp.Reg |MemRead8(pc.Reg++)));
cc[Z]=1;
cc[N]=0;
cc[V] = 0;
cc[C]=0;
CycleCounter+=6;
break;
case Page2: //10
P2_Opcode();
break;
case Page3: //11
P3_Opcode();
break;
case NOP_I: //12
CycleCounter+=2;
break;
case SYNC_I: //13
CycleCounter=CycleFor;
SyncWaiting=1;
break;
case HALT: //15
if (EmuState.Debugger.Halt_Enabled()) {
HaltedInsPending = 1;
VCC::ApplyHaltpoints(0);
EmuState.Debugger.Halt();
PC_REG -= 1;
} else {
CycleCounter+=2;
}
break;
case LBRA_R: //16
*spostword=MemRead16(pc.Reg);
pc.Reg+=2;
pc.Reg+=*spostword;
CycleCounter+=5;
break;
case LBSR_R: //17
*spostword=MemRead16(pc.Reg);
pc.Reg+=2;
s.Reg--;
MemWrite8(pc.B.lsb,s.Reg--);
MemWrite8(pc.B.msb,s.Reg);
pc.Reg+=*spostword;
CycleCounter+=9;
break;
case DAA_I: //19
// MessageBox(0,"DAA","Ok",0);
msn=(A_REG & 0xF0) ;
lsn=(A_REG & 0xF);
temp8=0;
if ( cc[H] || (lsn >9) )
temp8 |= 0x06;
if ( (msn>0x80) && (lsn>9))
temp8|=0x60;
if ( (msn>0x90) || cc[C] )
temp8|=0x60;
temp16= A_REG+temp8;
cc[C]|=((temp16 & 0x100)>>8);
A_REG= temp16 & 0xFF;
cc[N]= NTEST8(A_REG);
cc[Z]= ZTEST(A_REG);
CycleCounter+=2;
break;
case ORCC_M: //1A
postbyte=MemRead8(pc.Reg++);
temp8=getcc();
temp8 = (temp8 | postbyte);
setcc(temp8);
CycleCounter+=3;
break;
case ANDCC_M: //1C
postbyte=MemRead8(pc.Reg++);
temp8=getcc();
temp8 = (temp8 & postbyte);
setcc(temp8);
CycleCounter+=3;
break;
case SEX_I: //1D
// A_REG = ((signed char)B_REG < 0) ? 0xff : 0x00;
A_REG= 0-(B_REG>>7);
cc[Z]= ZTEST(D_REG);
cc[N]= NTEST16(D_REG);
CycleCounter+=2;
break;
case EXG_M: //1E
postbyte=MemRead8(pc.Reg++);
ccbits=getcc();
if ( ((postbyte & 0x80)>>4)==(postbyte & 0x08)) //Verify like size registers
{
if (postbyte & 0x08) //8 bit EXG
{
temp8= (*ureg8[((postbyte & 0x70) >> 4)]);
(*ureg8[((postbyte & 0x70) >> 4)]) = (*ureg8[postbyte & 0x07]);
(*ureg8[postbyte & 0x07])=temp8;
}
else // 16 bit EXG
{
temp16=(*xfreg16[((postbyte & 0x70) >> 4)]);
(*xfreg16[((postbyte & 0x70) >> 4)])=(*xfreg16[postbyte & 0x07]);
(*xfreg16[postbyte & 0x07])=temp16;
}
}
setcc(ccbits);
CycleCounter+=8;
break;
case TFR_M: //1F
postbyte=MemRead8(pc.Reg++);
Source= postbyte>>4;
Dest=postbyte & 15;
switch (Dest)
{
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
*xfreg16[Dest]=0xFFFF;
if ((Source == 12) | (Source == 13))
{
*xfreg16[Dest] = 0;
}
else if (Source <= 7)
{
//make sure the source is valud
if (xfreg16[Source])
{
*xfreg16[Dest] = *xfreg16[Source];
}
}
break;
case 8:
case 9:
case 10:
case 11:
case 14:
case 15:
ccbits=getcc();
*ureg8[Dest&7]=0xFF;
if ( (Source==12) | (Source==13) )
*ureg8[Dest&7]=0;
else
if (Source>7)
*ureg8[Dest&7]=*ureg8[Source&7];
setcc(ccbits);
break;
}
CycleCounter+=6;
break;
case BRA_R: //20
*spostbyte=MemRead8(pc.Reg++);
pc.Reg+=*spostbyte;
CycleCounter+=3;
break;
case BRN_R: //21
CycleCounter+=3;
pc.Reg++;
break;
case BHI_R: //22
if (!(cc[C] | cc[Z]))
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BLS_R: //23
if (cc[C] | cc[Z])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BHS_R: //24
if (!cc[C])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BLO_R: //25
if (cc[C])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BNE_R: //26
if (!cc[Z])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BEQ_R: //27
if (cc[Z])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BVC_R: //28
if (!cc[V])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BVS_R: //29
if ( cc[V])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BPL_R: //2A
if (!cc[N])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BMI_R: //2B
if ( cc[N])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BGE_R: //2C
if (! (cc[N] ^ cc[V]))
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BLT_R: //2D
if ( cc[V] ^ cc[N])
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BGT_R: //2E
if ( !( cc[Z] | (cc[N]^cc[V] ) ))
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case BLE_R: //2F
if ( cc[Z] | (cc[N]^cc[V]) )
pc.Reg+=(signed char)MemRead8(pc.Reg);
pc.Reg++;
CycleCounter+=3;
break;
case LEAX_X: //30
x.Reg=CalculateEA(MemRead8(pc.Reg++));
cc[Z]= ZTEST(x.Reg);
CycleCounter+=4;
break;
case LEAY_X: //31
y.Reg=CalculateEA(MemRead8(pc.Reg++));
cc[Z]= ZTEST(y.Reg);
CycleCounter+=4;
break;
case LEAS_X: //32
s.Reg=CalculateEA(MemRead8(pc.Reg++));
CycleCounter+=4;
break;
case LEAU_X: //33
u.Reg=CalculateEA(MemRead8(pc.Reg++));
CycleCounter+=4;
break;
case PSHS_M: //34
postbyte=MemRead8(pc.Reg++);
if (postbyte & 0x80)
{
MemWrite8( pc.B.lsb,--s.Reg);
MemWrite8( pc.B.msb,--s.Reg);
CycleCounter+=2;
}
if (postbyte & 0x40)
{
MemWrite8( u.B.lsb,--s.Reg);
MemWrite8( u.B.msb,--s.Reg);
CycleCounter+=2;
}
if (postbyte & 0x20)
{
MemWrite8( y.B.lsb,--s.Reg);
MemWrite8( y.B.msb,--s.Reg);
CycleCounter+=2;
}
if (postbyte & 0x10)
{
MemWrite8( x.B.lsb,--s.Reg);
MemWrite8( x.B.msb,--s.Reg);
CycleCounter+=2;
}
if (postbyte & 0x08)
{
MemWrite8( dp.B.msb,--s.Reg);
CycleCounter+=1;
}
if (postbyte & 0x04)
{
MemWrite8(B_REG,--s.Reg);
CycleCounter+=1;
}
if (postbyte & 0x02)
{
MemWrite8(A_REG,--s.Reg);
CycleCounter+=1;
}
if (postbyte & 0x01)
{
MemWrite8(getcc(),--s.Reg);
CycleCounter+=1;
}
CycleCounter+=5;
break;
case PULS_M: //35
postbyte=MemRead8(pc.Reg++);
if (postbyte & 0x01)
{
setcc(MemRead8(s.Reg++));
CycleCounter+=1;
}
if (postbyte & 0x02)
{
A_REG=MemRead8(s.Reg++);
CycleCounter+=1;
}
if (postbyte & 0x04)
{
B_REG=MemRead8(s.Reg++);
CycleCounter+=1;
}
if (postbyte & 0x08)
{
dp.B.msb=MemRead8(s.Reg++);
CycleCounter+=1;
}
if (postbyte & 0x10)
{
x.B.msb=MemRead8( s.Reg++);
x.B.lsb=MemRead8( s.Reg++);
CycleCounter+=2;
}
if (postbyte & 0x20)
{
y.B.msb=MemRead8( s.Reg++);
y.B.lsb=MemRead8( s.Reg++);
CycleCounter+=2;
}
if (postbyte & 0x40)
{
u.B.msb=MemRead8( s.Reg++);
u.B.lsb=MemRead8( s.Reg++);
CycleCounter+=2;
}
if (postbyte & 0x80)
{
pc.B.msb=MemRead8( s.Reg++);
pc.B.lsb=MemRead8( s.Reg++);
CycleCounter+=2;
}
CycleCounter+=5;
break;
case PSHU_M: //36
postbyte=MemRead8(pc.Reg++);
if (postbyte & 0x80)
{
MemWrite8( pc.B.lsb,--u.Reg);
MemWrite8( pc.B.msb,--u.Reg);
CycleCounter+=2;
}
if (postbyte & 0x40)
{
MemWrite8( s.B.lsb,--u.Reg);
MemWrite8( s.B.msb,--u.Reg);
CycleCounter+=2;
}
if (postbyte & 0x20)
{
MemWrite8( y.B.lsb,--u.Reg);
MemWrite8( y.B.msb,--u.Reg);
CycleCounter+=2;
}
if (postbyte & 0x10)
{
MemWrite8( x.B.lsb,--u.Reg);
MemWrite8( x.B.msb,--u.Reg);
CycleCounter+=2;
}
if (postbyte & 0x08)
{
MemWrite8( dp.B.msb,--u.Reg);
CycleCounter+=1;
}
if (postbyte & 0x04)
{
MemWrite8(B_REG,--u.Reg);
CycleCounter+=1;
}
if (postbyte & 0x02)
{
MemWrite8(A_REG,--u.Reg);
CycleCounter+=1;
}
if (postbyte & 0x01)
{
MemWrite8(getcc(),--u.Reg);
CycleCounter+=1;
}
CycleCounter+=5;
break;
case PULU_M: //37
postbyte=MemRead8(pc.Reg++);
if (postbyte & 0x01)
{
setcc(MemRead8(u.Reg++));
CycleCounter+=1;
}
if (postbyte & 0x02)
{
A_REG=MemRead8(u.Reg++);
CycleCounter+=1;
}
if (postbyte & 0x04)
{
B_REG=MemRead8(u.Reg++);
CycleCounter+=1;
}
if (postbyte & 0x08)
{
dp.B.msb=MemRead8(u.Reg++);
CycleCounter+=1;
}
if (postbyte & 0x10)
{
x.B.msb=MemRead8( u.Reg++);
x.B.lsb=MemRead8( u.Reg++);
CycleCounter+=2;
}
if (postbyte & 0x20)
{
y.B.msb=MemRead8( u.Reg++);
y.B.lsb=MemRead8( u.Reg++);
CycleCounter+=2;
}
if (postbyte & 0x40)
{
s.B.msb=MemRead8( u.Reg++);
s.B.lsb=MemRead8( u.Reg++);
CycleCounter+=2;
}
if (postbyte & 0x80)
{
pc.B.msb=MemRead8( u.Reg++);
pc.B.lsb=MemRead8( u.Reg++);
CycleCounter+=2;
}
CycleCounter+=5;
break;
case RTS_I: //39
pc.B.msb=MemRead8(s.Reg++);
pc.B.lsb=MemRead8(s.Reg++);
CycleCounter+=5;
break;
case ABX_I: //3A
x.Reg=x.Reg+B_REG;
CycleCounter+=3;
break;
case RTI_I: //3B
setcc(MemRead8(s.Reg++));
CycleCounter+=6;
if (cc[E])
{
A_REG=MemRead8(s.Reg++);
B_REG=MemRead8(s.Reg++);
dp.B.msb=MemRead8(s.Reg++);
x.B.msb=MemRead8(s.Reg++);
x.B.lsb=MemRead8(s.Reg++);
y.B.msb=MemRead8(s.Reg++);
y.B.lsb=MemRead8(s.Reg++);
u.B.msb=MemRead8(s.Reg++);
u.B.lsb=MemRead8(s.Reg++);
CycleCounter+=9;
}
pc.B.msb=MemRead8(s.Reg++);
pc.B.lsb=MemRead8(s.Reg++);
break;
case CWAI_I: //3C
postbyte=MemRead8(pc.Reg++);
ccbits=getcc();
ccbits = ccbits & postbyte;
setcc(ccbits);
CycleCounter=CycleFor;
SyncWaiting=1;
break;
case MUL_I: //3D
D_REG = A_REG * B_REG;
cc[C]= B_REG >0x7F;
cc[Z]= ZTEST(D_REG);
CycleCounter+=11;
break;
case RESET: //Undocumented
MC6809Reset();
break;
case SWI1_I: //3F
cc[E]=1;
MemWrite8( pc.B.lsb,--s.Reg);
MemWrite8( pc.B.msb,--s.Reg);
MemWrite8( u.B.lsb,--s.Reg);
MemWrite8( u.B.msb,--s.Reg);
MemWrite8( y.B.lsb,--s.Reg);
MemWrite8( y.B.msb,--s.Reg);
MemWrite8( x.B.lsb,--s.Reg);
MemWrite8( x.B.msb,--s.Reg);
MemWrite8( dp.B.msb,--s.Reg);
MemWrite8(B_REG,--s.Reg);
MemWrite8(A_REG,--s.Reg);
MemWrite8(getcc(),--s.Reg);
pc.Reg=MemRead16(VSWI);
CycleCounter+=19;
cc[I]=1;
cc[F]=1;
break;
case NEGA_I: //40
temp8= 0-A_REG;
cc[C]= temp8>0;
cc[V]= A_REG==0x80; //cc[C] ^ ((A_REG^temp8)>>7);
cc[N]= NTEST8(temp8);
cc[Z]= ZTEST(temp8);
A_REG= temp8;
CycleCounter+=2;
break;
case COMA_I: //43
A_REG= 0xFF- A_REG;
cc[Z]= ZTEST(A_REG);
cc[N]= NTEST8(A_REG);
cc[C]= 1;
cc[V]= 0;
CycleCounter+=2;
break;
case LSRA_I: //44
cc[C]= A_REG & 1;
A_REG= A_REG>>1;
cc[Z]= ZTEST(A_REG);
cc[N]= 0;
CycleCounter+=2;
break;
case RORA_I: //46
postbyte=cc[C]<<7;
cc[C]= A_REG & 1;
A_REG= (A_REG>>1) | postbyte;
cc[Z]= ZTEST(A_REG);
cc[N]= NTEST8(A_REG);
CycleCounter+=2;
break;
case ASRA_I: //47
cc[C]= A_REG & 1;
A_REG= (A_REG & 0x80) | (A_REG >> 1);
cc[Z]= ZTEST(A_REG);
cc[N]= NTEST8(A_REG);
CycleCounter+=2;
break;
case ASLA_I: //48 JF
cc[C]= A_REG > 0x7F;
cc[V]= cc[C] ^((A_REG & 0x40)>>6);
A_REG= A_REG<<1;
cc[N]= NTEST8(A_REG);
cc[Z]= ZTEST(A_REG);
CycleCounter+=2;