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Merge #1306
1306: Update embedded-hal r=Dirbaio a=Dirbaio - [x] Wait for merge rust-embedded/embedded-hal#443 - [x] Wait for release - [x] embassy-embedded-hal - [x] embassy-nrf - [x] embassy-stm32 - [x] embassy-rp Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2 parents f3ec608 + 8db8c9e commit 832fa8f

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-595
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27 files changed

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‎embassy-embedded-hal/Cargo.toml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,8 +19,8 @@ nightly = ["embedded-hal-async", "embedded-storage-async"]
1919
[dependencies]
2020
embassy-sync = { version = "0.1.0", path = "../embassy-sync" }
2121
embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
22-
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.9" }
23-
embedded-hal-async = { version = "=0.2.0-alpha.0", optional = true }
22+
embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-alpha.10" }
23+
embedded-hal-async = { version = "=0.2.0-alpha.1", optional = true }
2424
embedded-storage = "0.3.0"
2525
embedded-storage-async = { version = "0.4.0", optional = true }
2626
nb = "1.0.0"

‎embassy-embedded-hal/src/adapter.rs

Lines changed: 9 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -36,27 +36,22 @@ where
3636
E: embedded_hal_1::i2c::Error + 'static,
3737
T: blocking::i2c::WriteRead<Error = E> + blocking::i2c::Read<Error = E> + blocking::i2c::Write<Error = E>,
3838
{
39-
async fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Result<(), Self::Error> {
40-
self.wrapped.read(address, buffer)
39+
async fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
40+
self.wrapped.read(address, read)
4141
}
4242

43-
async fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Result<(), Self::Error> {
44-
self.wrapped.write(address, bytes)
43+
async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
44+
self.wrapped.write(address, write)
4545
}
4646

47-
async fn write_read<'a>(
48-
&'a mut self,
49-
address: u8,
50-
bytes: &'a [u8],
51-
buffer: &'a mut [u8],
52-
) -> Result<(), Self::Error> {
53-
self.wrapped.write_read(address, bytes, buffer)
47+
async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
48+
self.wrapped.write_read(address, write, read)
5449
}
5550

56-
async fn transaction<'a, 'b>(
57-
&'a mut self,
51+
async fn transaction(
52+
&mut self,
5853
address: u8,
59-
operations: &'a mut [embedded_hal_async::i2c::Operation<'b>],
54+
operations: &mut [embedded_hal_1::i2c::Operation<'_>],
6055
) -> Result<(), Self::Error> {
6156
let _ = address;
6257
let _ = operations;

‎embassy-embedded-hal/src/lib.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
#![cfg_attr(not(feature = "std"), no_std)]
22
#![cfg_attr(
33
feature = "nightly",
4-
feature(type_alias_impl_trait, async_fn_in_trait, impl_trait_projections)
4+
feature(type_alias_impl_trait, async_fn_in_trait, impl_trait_projections, try_blocks)
55
)]
66
#![cfg_attr(feature = "nightly", allow(incomplete_features))]
77
#![warn(missing_docs)]

‎embassy-embedded-hal/src/shared_bus/asynch/i2c.rs

Lines changed: 19 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -54,35 +54,35 @@ where
5454
M: RawMutex + 'static,
5555
BUS: i2c::I2c + 'static,
5656
{
57-
async fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
57+
async fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
5858
let mut bus = self.bus.lock().await;
59-
bus.read(address, buffer).await.map_err(I2cDeviceError::I2c)?;
59+
bus.read(address, read).await.map_err(I2cDeviceError::I2c)?;
6060
Ok(())
6161
}
6262

63-
async fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
63+
async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
6464
let mut bus = self.bus.lock().await;
65-
bus.write(address, bytes).await.map_err(I2cDeviceError::I2c)?;
65+
bus.write(address, write).await.map_err(I2cDeviceError::I2c)?;
6666
Ok(())
6767
}
6868

69-
async fn write_read<'a>(
70-
&'a mut self,
69+
async fn write_read(
70+
&mut self,
7171
address: u8,
72-
wr_buffer: &'a [u8],
73-
rd_buffer: &'a mut [u8],
72+
write: &[u8],
73+
read: &mut [u8],
7474
) -> Result<(), I2cDeviceError<BUS::Error>> {
7575
let mut bus = self.bus.lock().await;
76-
bus.write_read(address, wr_buffer, rd_buffer)
76+
bus.write_read(address, write, read)
7777
.await
7878
.map_err(I2cDeviceError::I2c)?;
7979
Ok(())
8080
}
8181

82-
async fn transaction<'a, 'b>(
83-
&'a mut self,
82+
async fn transaction(
83+
&mut self,
8484
address: u8,
85-
operations: &'a mut [embedded_hal_async::i2c::Operation<'b>],
85+
operations: &mut [embedded_hal_async::i2c::Operation<'_>],
8686
) -> Result<(), I2cDeviceError<BUS::Error>> {
8787
let _ = address;
8888
let _ = operations;
@@ -121,25 +121,25 @@ where
121121
M: RawMutex + 'static,
122122
BUS: i2c::I2c + SetConfig + 'static,
123123
{
124-
async fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
124+
async fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
125125
let mut bus = self.bus.lock().await;
126126
bus.set_config(&self.config);
127127
bus.read(address, buffer).await.map_err(I2cDeviceError::I2c)?;
128128
Ok(())
129129
}
130130

131-
async fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
131+
async fn write(&mut self, address: u8, bytes: &[u8]) -> Result<(), I2cDeviceError<BUS::Error>> {
132132
let mut bus = self.bus.lock().await;
133133
bus.set_config(&self.config);
134134
bus.write(address, bytes).await.map_err(I2cDeviceError::I2c)?;
135135
Ok(())
136136
}
137137

138-
async fn write_read<'a>(
139-
&'a mut self,
138+
async fn write_read(
139+
&mut self,
140140
address: u8,
141-
wr_buffer: &'a [u8],
142-
rd_buffer: &'a mut [u8],
141+
wr_buffer: &[u8],
142+
rd_buffer: &mut [u8],
143143
) -> Result<(), I2cDeviceError<BUS::Error>> {
144144
let mut bus = self.bus.lock().await;
145145
bus.set_config(&self.config);
@@ -149,11 +149,7 @@ where
149149
Ok(())
150150
}
151151

152-
async fn transaction<'a, 'b>(
153-
&'a mut self,
154-
address: u8,
155-
operations: &'a mut [embedded_hal_async::i2c::Operation<'b>],
156-
) -> Result<(), I2cDeviceError<BUS::Error>> {
152+
async fn transaction(&mut self, address: u8, operations: &mut [i2c::Operation<'_>]) -> Result<(), Self::Error> {
157153
let _ = address;
158154
let _ = operations;
159155
todo!()

‎embassy-embedded-hal/src/shared_bus/asynch/spi.rs

Lines changed: 145 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -25,12 +25,11 @@
2525
//! let spi_dev2 = SpiDevice::new(spi_bus, cs_pin2);
2626
//! let display2 = ST7735::new(spi_dev2, dc2, rst2, Default::default(), 160, 128);
2727
//! ```
28-
use core::future::Future;
2928
3029
use embassy_sync::blocking_mutex::raw::RawMutex;
3130
use embassy_sync::mutex::Mutex;
3231
use embedded_hal_1::digital::OutputPin;
33-
use embedded_hal_1::spi::ErrorType;
32+
use embedded_hal_1::spi::Operation;
3433
use embedded_hal_async::spi;
3534

3635
use crate::shared_bus::SpiDeviceError;
@@ -57,33 +56,92 @@ where
5756
type Error = SpiDeviceError<BUS::Error, CS::Error>;
5857
}
5958

60-
unsafe impl<M, BUS, CS> spi::SpiDevice for SpiDevice<'_, M, BUS, CS>
59+
impl<M, BUS, CS> spi::SpiDeviceRead for SpiDevice<'_, M, BUS, CS>
6160
where
62-
M: RawMutex + 'static,
63-
BUS: spi::SpiBusFlush + 'static,
61+
M: RawMutex,
62+
BUS: spi::SpiBusRead,
6463
CS: OutputPin,
6564
{
66-
type Bus = BUS;
65+
async fn read_transaction(&mut self, operations: &mut [&mut [u8]]) -> Result<(), Self::Error> {
66+
let mut bus = self.bus.lock().await;
67+
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
68+
69+
let op_res: Result<(), BUS::Error> = try {
70+
for buf in operations {
71+
bus.read(buf).await?;
72+
}
73+
};
74+
75+
// On failure, it's important to still flush and deassert CS.
76+
let flush_res = bus.flush().await;
77+
let cs_res = self.cs.set_high();
6778

68-
async fn transaction<R, F, Fut>(&mut self, f: F) -> Result<R, Self::Error>
69-
where
70-
F: FnOnce(*mut Self::Bus) -> Fut,
71-
Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>>,
72-
{
79+
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
80+
flush_res.map_err(SpiDeviceError::Spi)?;
81+
cs_res.map_err(SpiDeviceError::Cs)?;
82+
83+
Ok(op_res)
84+
}
85+
}
86+
87+
impl<M, BUS, CS> spi::SpiDeviceWrite for SpiDevice<'_, M, BUS, CS>
88+
where
89+
M: RawMutex,
90+
BUS: spi::SpiBusWrite,
91+
CS: OutputPin,
92+
{
93+
async fn write_transaction(&mut self, operations: &[&[u8]]) -> Result<(), Self::Error> {
7394
let mut bus = self.bus.lock().await;
7495
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
7596

76-
let f_res = f(&mut *bus).await;
97+
let op_res: Result<(), BUS::Error> = try {
98+
for buf in operations {
99+
bus.write(buf).await?;
100+
}
101+
};
77102

78103
// On failure, it's important to still flush and deassert CS.
79104
let flush_res = bus.flush().await;
80105
let cs_res = self.cs.set_high();
81106

82-
let f_res = f_res.map_err(SpiDeviceError::Spi)?;
107+
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
83108
flush_res.map_err(SpiDeviceError::Spi)?;
84109
cs_res.map_err(SpiDeviceError::Cs)?;
85110

86-
Ok(f_res)
111+
Ok(op_res)
112+
}
113+
}
114+
115+
impl<M, BUS, CS> spi::SpiDevice for SpiDevice<'_, M, BUS, CS>
116+
where
117+
M: RawMutex,
118+
BUS: spi::SpiBus,
119+
CS: OutputPin,
120+
{
121+
async fn transaction(&mut self, operations: &mut [spi::Operation<'_, u8>]) -> Result<(), Self::Error> {
122+
let mut bus = self.bus.lock().await;
123+
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
124+
125+
let op_res: Result<(), BUS::Error> = try {
126+
for op in operations {
127+
match op {
128+
Operation::Read(buf) => bus.read(buf).await?,
129+
Operation::Write(buf) => bus.write(buf).await?,
130+
Operation::Transfer(read, write) => bus.transfer(read, write).await?,
131+
Operation::TransferInPlace(buf) => bus.transfer_in_place(buf).await?,
132+
}
133+
}
134+
};
135+
136+
// On failure, it's important to still flush and deassert CS.
137+
let flush_res = bus.flush().await;
138+
let cs_res = self.cs.set_high();
139+
140+
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
141+
flush_res.map_err(SpiDeviceError::Spi)?;
142+
cs_res.map_err(SpiDeviceError::Cs)?;
143+
144+
Ok(op_res)
87145
}
88146
}
89147

@@ -114,33 +172,94 @@ where
114172
type Error = SpiDeviceError<BUS::Error, CS::Error>;
115173
}
116174

117-
unsafe impl<M, BUS, CS> spi::SpiDevice for SpiDeviceWithConfig<'_, M, BUS, CS>
175+
impl<M, BUS, CS> spi::SpiDeviceWrite for SpiDeviceWithConfig<'_, M, BUS, CS>
176+
where
177+
M: RawMutex,
178+
BUS: spi::SpiBusWrite + SetConfig,
179+
CS: OutputPin,
180+
{
181+
async fn write_transaction(&mut self, operations: &[&[u8]]) -> Result<(), Self::Error> {
182+
let mut bus = self.bus.lock().await;
183+
bus.set_config(&self.config);
184+
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
185+
186+
let op_res: Result<(), BUS::Error> = try {
187+
for buf in operations {
188+
bus.write(buf).await?;
189+
}
190+
};
191+
192+
// On failure, it's important to still flush and deassert CS.
193+
let flush_res = bus.flush().await;
194+
let cs_res = self.cs.set_high();
195+
196+
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
197+
flush_res.map_err(SpiDeviceError::Spi)?;
198+
cs_res.map_err(SpiDeviceError::Cs)?;
199+
200+
Ok(op_res)
201+
}
202+
}
203+
204+
impl<M, BUS, CS> spi::SpiDeviceRead for SpiDeviceWithConfig<'_, M, BUS, CS>
118205
where
119-
M: RawMutex + 'static,
120-
BUS: spi::SpiBusFlush + SetConfig + 'static,
206+
M: RawMutex,
207+
BUS: spi::SpiBusRead + SetConfig,
121208
CS: OutputPin,
122209
{
123-
type Bus = BUS;
210+
async fn read_transaction(&mut self, operations: &mut [&mut [u8]]) -> Result<(), Self::Error> {
211+
let mut bus = self.bus.lock().await;
212+
bus.set_config(&self.config);
213+
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
214+
215+
let op_res: Result<(), BUS::Error> = try {
216+
for buf in operations {
217+
bus.read(buf).await?;
218+
}
219+
};
220+
221+
// On failure, it's important to still flush and deassert CS.
222+
let flush_res = bus.flush().await;
223+
let cs_res = self.cs.set_high();
224+
225+
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
226+
flush_res.map_err(SpiDeviceError::Spi)?;
227+
cs_res.map_err(SpiDeviceError::Cs)?;
228+
229+
Ok(op_res)
230+
}
231+
}
124232

125-
async fn transaction<R, F, Fut>(&mut self, f: F) -> Result<R, Self::Error>
126-
where
127-
F: FnOnce(*mut Self::Bus) -> Fut,
128-
Fut: Future<Output = Result<R, <Self::Bus as ErrorType>::Error>>,
129-
{
233+
impl<M, BUS, CS> spi::SpiDevice for SpiDeviceWithConfig<'_, M, BUS, CS>
234+
where
235+
M: RawMutex,
236+
BUS: spi::SpiBus + SetConfig,
237+
CS: OutputPin,
238+
{
239+
async fn transaction(&mut self, operations: &mut [spi::Operation<'_, u8>]) -> Result<(), Self::Error> {
130240
let mut bus = self.bus.lock().await;
131241
bus.set_config(&self.config);
132242
self.cs.set_low().map_err(SpiDeviceError::Cs)?;
133243

134-
let f_res = f(&mut *bus).await;
244+
let op_res: Result<(), BUS::Error> = try {
245+
for op in operations {
246+
match op {
247+
Operation::Read(buf) => bus.read(buf).await?,
248+
Operation::Write(buf) => bus.write(buf).await?,
249+
Operation::Transfer(read, write) => bus.transfer(read, write).await?,
250+
Operation::TransferInPlace(buf) => bus.transfer_in_place(buf).await?,
251+
}
252+
}
253+
};
135254

136255
// On failure, it's important to still flush and deassert CS.
137256
let flush_res = bus.flush().await;
138257
let cs_res = self.cs.set_high();
139258

140-
let f_res = f_res.map_err(SpiDeviceError::Spi)?;
259+
let op_res = op_res.map_err(SpiDeviceError::Spi)?;
141260
flush_res.map_err(SpiDeviceError::Spi)?;
142261
cs_res.map_err(SpiDeviceError::Cs)?;
143262

144-
Ok(f_res)
263+
Ok(op_res)
145264
}
146265
}

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