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cmd/asm, cmd/internal/obj/ppc64: Add vector scalar (VSX) registers and instructions
The current implementation for Power architecture does not include the vector scalar (VSX) registers. This adds the 63 VSX registers and the most commonly used instructions: load/store VSX vector/scalar, move to/from VSR, logical operations, select, merge, splat, permute, shift, FP-FP conversion, FP-integer conversion and integer-FP conversion. Change-Id: I0f7572d2359fe7f3ea0124a1eb1b0bebab33649e Reviewed-on: https://go-review.googlesource.com/30510 Reviewed-by: Lynn Boger <laboger@linux.vnet.ibm.com> Reviewed-by: David Chase <drchase@google.com> Run-TryBot: David Chase <drchase@google.com> TryBot-Result: Gobot Gobot <gobot@golang.org>
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‎src/cmd/asm/internal/arch/arch.go

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -322,6 +322,9 @@ func archPPC64() *Arch {
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for i := ppc64.REG_V0; i <= ppc64.REG_V31; i++ {
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register[obj.Rconv(i)] = int16(i)
324324
}
325+
for i := ppc64.REG_VS0; i <= ppc64.REG_VS63; i++ {
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register[obj.Rconv(i)] = int16(i)
327+
}
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for i := ppc64.REG_CR0; i <= ppc64.REG_CR7; i++ {
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register[obj.Rconv(i)] = int16(i)
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}

‎src/cmd/asm/internal/arch/ppc64.go

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -77,6 +77,10 @@ func ppc64RegisterNumber(name string, n int16) (int16, bool) {
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if 0 <= n && n <= 7 {
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return ppc64.REG_CR0 + n, true
7979
}
80+
case "VS":
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if 0 <= n && n <= 63 {
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return ppc64.REG_VS0 + n, true
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}
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case "V":
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if 0 <= n && n <= 31 {
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return ppc64.REG_V0 + n, true

‎src/cmd/asm/internal/asm/operand_test.go

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -340,6 +340,70 @@ var ppc64OperandTests = []operandTest{
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{"6(PC)", "6(PC)"},
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{"CR7", "CR7"},
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{"CTR", "CTR"},
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{"VS0", "VS0"},
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{"VS1", "VS1"},
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{"VS2", "VS2"},
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{"VS3", "VS3"},
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{"VS4", "VS4"},
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{"VS5", "VS5"},
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{"VS6", "VS6"},
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{"VS7", "VS7"},
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{"VS8", "VS8"},
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{"VS9", "VS9"},
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{"VS10", "VS10"},
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{"VS11", "VS11"},
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{"VS12", "VS12"},
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{"VS13", "VS13"},
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{"VS14", "VS14"},
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{"VS15", "VS15"},
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{"VS16", "VS16"},
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{"VS17", "VS17"},
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{"VS18", "VS18"},
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{"VS19", "VS19"},
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{"VS20", "VS20"},
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{"VS21", "VS21"},
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{"VS22", "VS22"},
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{"VS23", "VS23"},
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{"VS24", "VS24"},
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{"VS25", "VS25"},
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{"VS26", "VS26"},
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{"VS27", "VS27"},
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{"VS28", "VS28"},
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{"VS29", "VS29"},
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{"VS30", "VS30"},
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{"VS31", "VS31"},
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{"VS32", "VS32"},
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{"VS33", "VS33"},
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{"VS34", "VS34"},
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{"VS35", "VS35"},
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{"VS36", "VS36"},
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{"VS37", "VS37"},
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{"VS38", "VS38"},
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{"VS39", "VS39"},
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{"VS40", "VS40"},
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{"VS41", "VS41"},
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{"VS42", "VS42"},
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{"VS43", "VS43"},
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{"VS44", "VS44"},
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{"VS45", "VS45"},
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{"VS46", "VS46"},
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{"VS47", "VS47"},
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{"VS48", "VS48"},
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{"VS49", "VS49"},
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{"VS50", "VS50"},
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{"VS51", "VS51"},
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{"VS52", "VS52"},
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{"VS53", "VS53"},
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{"VS54", "VS54"},
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{"VS55", "VS55"},
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{"VS56", "VS56"},
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{"VS57", "VS57"},
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{"VS58", "VS58"},
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{"VS59", "VS59"},
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{"VS60", "VS60"},
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{"VS61", "VS61"},
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{"VS62", "VS62"},
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{"VS63", "VS63"},
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{"V0", "V0"},
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{"V1", "V1"},
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{"V2", "V2"},

‎src/cmd/asm/internal/asm/testdata/ppc64.s

Lines changed: 134 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -677,7 +677,7 @@ label1:
677677

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// Described as:
679679
// <instruction type>, <instruction format>
680-
// <golang asm operand order> produces
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// <go asm operand order> produces
681681
// <Power ISA operand order>
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// Vector load, VX-form
@@ -880,6 +880,139 @@ label1:
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VSHASIGMAW $15, V1, $1, V0
881881
VSHASIGMAD $15, V1, $1, V0
882882

883+
// VSX instructions
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// Described as:
885+
// <instruction type>, <instruction format>
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// <go asm operand order> produces
887+
// <Power ISA operand order>
888+
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// VSX load, XX1-form
890+
// <MNEMONIC> (RB)(RA*1),XT produces
891+
// <mnemonic> XT,RA,RB
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LXVD2X (R1)(R2*1), VS0
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LXVDSX (R1)(R2*1), VS0
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LXVW4X (R1)(R2*1), VS0
895+
LXSDX (R1)(R2*1), VS0
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LXSIWAX (R1)(R2*1), VS0
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LXSIWZX (R1)(R2*1), VS0
898+
899+
// VSX store, XX1-form
900+
// <MNEMONIC> XS,(RB)(RA*1) produces
901+
// <mnemonic> XS,RA,RB
902+
STXVD2X VS63, (R1)(R2*1)
903+
STXVW4X VS63, (R1)(R2*1)
904+
STXSDX VS63, (R1)(R2*1)
905+
STXSIWX VS63, (R1)(R2*1)
906+
907+
// VSX move from VSR, XX1-form
908+
// <MNEMONIC> XS,RA produces
909+
// <mnemonic> RA,XS
910+
MFVSRD VS0, R1
911+
MFVSRWZ VS33, R1
912+
913+
// VSX move to VSR, XX1-form
914+
// <MNEMONIC> RA,XT produces
915+
// <mnemonic> XT,RA
916+
MTVSRD R1, VS0
917+
MTVSRWA R1, VS31
918+
MTVSRWZ R1, VS63
919+
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// VSX AND, XX3-form
921+
// <MNEMONIC> XA,XB,XT produces
922+
// <mnemonic> XT,XA,XB
923+
XXLANDQ VS0,VS1,VS32
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XXLANDC VS0,VS1,VS32
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XXLEQV VS0,VS1,VS32
926+
XXLNAND VS0,VS1,VS32
927+
928+
// VSX OR, XX3-form
929+
// <MNEMONIC> XA,XB,XT produces
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// <mnemonic> XT,XA,XB
931+
XXLORC VS0,VS1,VS32
932+
XXLNOR VS0,VS1,VS32
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XXLORQ VS0,VS1,VS32
934+
XXLXOR VS0,VS1,VS32
935+
936+
// VSX select, XX4-form
937+
// <MNEMONIC> XA,XB,XC,XT produces
938+
// <mnemonic> XT,XA,XB,XC
939+
XXSEL VS0,VS1,VS3,VS32
940+
941+
// VSX merge, XX3-form
942+
// <MNEMONIC> XA,XB,XT produces
943+
// <mnemonic> XT,XA,XB
944+
XXMRGHW VS0,VS1,VS32
945+
XXMRGLW VS0,VS1,VS32
946+
947+
// VSX splat, XX2-form
948+
// <MNEMONIC> XB,UIM,XT produces
949+
// <mnemonic> XT,XB,UIM
950+
XXSPLTW VS0,$3,VS32
951+
952+
// VSX permute, XX3-form
953+
// <MNEMONIC> XA,XB,DM,XT produces
954+
// <mnemonic> XT,XA,XB,DM
955+
XXPERMDI VS0,VS1,$3,VS32
956+
957+
// VSX shift, XX3-form
958+
// <MNEMONIC> XA,XB,SHW,XT produces
959+
// <mnemonic> XT,XA,XB,SHW
960+
XXSLDWI VS0,VS1,$3,VS32
961+
962+
// VSX scalar FP-FP conversion, XX2-form
963+
// <MNEMONIC> XB,XT produces
964+
// <mnemonic> XT,XB
965+
XSCVDPSP VS0,VS32
966+
XSCVSPDP VS0,VS32
967+
XSCVDPSPN VS0,VS32
968+
XSCVSPDPN VS0,VS32
969+
970+
// VSX vector FP-FP conversion, XX2-form
971+
// <MNEMONIC> XB,XT produces
972+
// <mnemonic> XT,XB
973+
XVCVDPSP VS0,VS32
974+
XVCVSPDP VS0,VS32
975+
976+
// VSX scalar FP-integer conversion, XX2-form
977+
// <MNEMONIC> XB,XT produces
978+
// <mnemonic> XT,XB
979+
XSCVDPSXDS VS0,VS32
980+
XSCVDPSXWS VS0,VS32
981+
XSCVDPUXDS VS0,VS32
982+
XSCVDPUXWS VS0,VS32
983+
984+
// VSX scalar integer-FP conversion, XX2-form
985+
// <MNEMONIC> XB,XT produces
986+
// <mnemonic> XT,XB
987+
XSCVSXDDP VS0,VS32
988+
XSCVUXDDP VS0,VS32
989+
XSCVSXDSP VS0,VS32
990+
XSCVUXDSP VS0,VS32
991+
992+
// VSX vector FP-integer conversion, XX2-form
993+
// <MNEMONIC> XB,XT produces
994+
// <mnemonic> XT,XB
995+
XVCVDPSXDS VS0,VS32
996+
XVCVDPSXWS VS0,VS32
997+
XVCVDPUXDS VS0,VS32
998+
XVCVDPUXWS VS0,VS32
999+
XVCVSPSXDS VS0,VS32
1000+
XVCVSPSXWS VS0,VS32
1001+
XVCVSPUXDS VS0,VS32
1002+
XVCVSPUXWS VS0,VS32
1003+
1004+
// VSX scalar integer-FP conversion, XX2-form
1005+
// <MNEMONIC> XB,XT produces
1006+
// <mnemonic> XT,XB
1007+
XVCVSXDDP VS0,VS32
1008+
XVCVSXWDP VS0,VS32
1009+
XVCVUXDDP VS0,VS32
1010+
XVCVUXWDP VS0,VS32
1011+
XVCVSXDSP VS0,VS32
1012+
XVCVSXWSP VS0,VS32
1013+
XVCVUXDSP VS0,VS32
1014+
XVCVUXWSP VS0,VS32
1015+
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//
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// NOP
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//

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