dff.vp

/*
 This is a Genesis wrapper of DW pipeline regs with en singal
 */

/* ***************************************************************************
 * Change bar:
 * -----------
 * Date           Author    Description
 * Sep 20, 2012   jingpu    init version
 *                          
 * ***************************************************************************/

/*******************************************************************************
 * PARAMETERIZATION
 * ****************************************************************************/
//; # module parameters
//; my $width           = parameter(Name=>'BitWidth', 
//;                                 Val=>64, Min=>1, Step=>1, 
//;                                 Doc=>"Signal bit widths");
//; my $pipe_depth      = parameter(Name=>'PipelineDepth', 
//;                                 Val=>1, Min=>0, Step=>1, 
//;                                 Doc=>"Pipeline depth");
//; my $retime_Status   = parameter(Name=>'Retime' ,
//;                                 Val=>'NO' , List=>[ 'YES' , 'NO' ] , 
//;                                 Doc=>"Pipeline Is Retimeable" ) ;

module `mname` (
		input logic [`$width-1`:0]  in, 
		input logic 		    clk, reset, en, 
		output logic [`$width-1`:0] out
		);

   
   /* synopsys dc_tcl_script_begin
    set_ungroup [current_design] true
    set_flatten true -effort high -phase true -design [current_design]
    //; #   https://solvnet.synopsys.com/dow_retrieve/G-2012.03/manpages/syn2/set_dont_retime.html
    //; if( $retime_Status eq 'YES' ){
    set_dont_retime [current_design] false 
    set_optimize_registers true -design [current_design]
    //; } elsif (  $retime_Status eq 'NO' ){
    set_dont_retime [current_design] true
    set_optimize_registers false -design [current_design]
    //; } else {
    //;    self->error( "Unexpected branch condition in retiming elaboration...\n" ) ;   
   //; }
    */
   
   //; if ($pipe_depth>0) {
   //   DW03_pipe_reg #(`$pipe_depth`,`$width`) dff ( .A(in) , .clk(clk) , .B(out) ) ;
   DW_pl_reg #(.stages(`$pipe_depth+1`),.in_reg(0),.out_reg(0),.width(`$width`),.rst_mode(0)) dff ( .data_in(in) , .clk(clk) , .data_out(out), .rst_n(!reset), .enable({`$pipe_depth`{en}}) );
   //; } else {
   //    assign out = in;
   assign out = in & (~{`$width`{reset}});
   //; }
   
endmodule