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[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
Per #80143, we can remove the extra line break when there is no instruction.
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50 files changed

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‎llvm/lib/CodeGen/MIRPrinter.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -728,7 +728,7 @@ void MIPrinter::print(const MachineBasicBlock &MBB) {
728728
HasLineAttributes = true;
729729
}
730730

731-
if (HasLineAttributes)
731+
if (HasLineAttributes && !MBB.empty())
732732
OS << "\n";
733733
bool IsInBundle = false;
734734
for (const MachineInstr &MI : MBB.instrs()) {

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll

+19-26
Original file line numberDiff line numberDiff line change
@@ -136,9 +136,8 @@ define i32 @test_cfg_remap_multiple_preds(i32 %in) {
136136
; CHECK-NEXT: {{ $}}
137137
; CHECK-NEXT: bb.2.odd:
138138
; CHECK-NEXT: successors:
139-
; CHECK: {{ $}}
140-
; CHECK: {{ $}}
141-
; CHECK: bb.3.next:
139+
; CHECK-NEXT: {{ $}}
140+
; CHECK-NEXT: bb.3.next:
142141
; CHECK-NEXT: G_BR %bb.5
143142
; CHECK-NEXT: {{ $}}
144143
; CHECK-NEXT: bb.4.other:
@@ -1147,25 +1146,20 @@ define void @jt_2_tables_phi_edge_from_second() {
11471146
; CHECK-NEXT: {{ $}}
11481147
; CHECK-NEXT: bb.2.if.then:
11491148
; CHECK-NEXT: successors:
1150-
; CHECK: {{ $}}
1151-
; CHECK: {{ $}}
1152-
; CHECK: bb.3.sw.bb2.i41:
1149+
; CHECK-NEXT: {{ $}}
1150+
; CHECK-NEXT: bb.3.sw.bb2.i41:
1151+
; CHECK-NEXT: successors:
1152+
; CHECK-NEXT: {{ $}}
1153+
; CHECK-NEXT: bb.4.sw.bb7.i44:
11531154
; CHECK-NEXT: successors:
1154-
; CHECK: {{ $}}
1155-
; CHECK: {{ $}}
1156-
; CHECK: bb.4.sw.bb7.i44:
1155+
; CHECK-NEXT: {{ $}}
1156+
; CHECK-NEXT: bb.5.sw.bb8.i45:
11571157
; CHECK-NEXT: successors:
1158-
; CHECK: {{ $}}
1159-
; CHECK: {{ $}}
1160-
; CHECK: bb.5.sw.bb8.i45:
1158+
; CHECK-NEXT: {{ $}}
1159+
; CHECK-NEXT: bb.6.sw.bb13.i47:
11611160
; CHECK-NEXT: successors:
1162-
; CHECK: {{ $}}
1163-
; CHECK: {{ $}}
1164-
; CHECK: bb.6.sw.bb13.i47:
1165-
; CHECK: successors:
1166-
; CHECK: {{ $}}
1167-
; CHECK: {{ $}}
1168-
; CHECK: bb.7.sw.bb14.i48:
1161+
; CHECK-NEXT: {{ $}}
1162+
; CHECK-NEXT: bb.7.sw.bb14.i48:
11691163
; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C5]]
11701164
; CHECK-NEXT: G_BRCOND [[ICMP5]](s1), %bb.10
11711165
; CHECK-NEXT: G_BR %bb.24
@@ -1207,9 +1201,8 @@ define void @jt_2_tables_phi_edge_from_second() {
12071201
; CHECK-NEXT: {{ $}}
12081202
; CHECK-NEXT: bb.8.sw.default.i49:
12091203
; CHECK-NEXT: successors:
1210-
; CHECK: {{ $}}
1211-
; CHECK: {{ $}}
1212-
; CHECK: bb.9.sw.bb1.i:
1204+
; CHECK-NEXT: {{ $}}
1205+
; CHECK-NEXT: bb.9.sw.bb1.i:
12131206
; CHECK-NEXT: G_BR %bb.16
12141207
; CHECK-NEXT: {{ $}}
12151208
; CHECK-NEXT: bb.10.sw.bb4.i:
@@ -1237,8 +1230,8 @@ define void @jt_2_tables_phi_edge_from_second() {
12371230
; CHECK-NEXT: {{ $}}
12381231
; CHECK-NEXT: bb.17.while.body:
12391232
; CHECK-NEXT: successors:
1240-
; CHECK: {{ $}}
1241-
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
1233+
; CHECK-NEXT: {{ $}}
1234+
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
12421235
; CHECK-NEXT: BL @jt_2_tables_phi_edge_from_second, csr_aarch64_aapcs, implicit-def $lr, implicit $sp
12431236
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
12441237
; CHECK-NEXT: {{ $}}
@@ -1463,8 +1456,8 @@ define i1 @i1_value_cmp_is_signed(i1) {
14631456
; CHECK-NEXT: {{ $}}
14641457
; CHECK-NEXT: bb.2.BadValue:
14651458
; CHECK-NEXT: successors:
1466-
; CHECK: {{ $}}
1467-
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
1459+
; CHECK-NEXT: {{ $}}
1460+
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
14681461
; CHECK-NEXT: BL @bar, csr_aarch64_aapcs, implicit-def $lr, implicit $sp
14691462
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
14701463
; CHECK-NEXT: {{ $}}

‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll

-22
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,6 @@ define i32 @val_compare_and_swap(ptr %p, i32 %cmp, i32 %new) {
88
; CHECK-NEXT: successors: %bb.1(0x80000000)
99
; CHECK-NEXT: liveins: $w1, $w2, $x0
1010
; CHECK-NEXT: {{ $}}
11-
; CHECK-NEXT: {{ $}}
1211
; CHECK-NEXT: bb.1.cmpxchg.start:
1312
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
1413
; CHECK-NEXT: liveins: $w1, $w2, $x0
@@ -88,7 +87,6 @@ define i32 @val_compare_and_swap_rel(ptr %p, i32 %cmp, i32 %new) {
8887
; CHECK-NEXT: successors: %bb.1(0x80000000)
8988
; CHECK-NEXT: liveins: $w1, $w2, $x0
9089
; CHECK-NEXT: {{ $}}
91-
; CHECK-NEXT: {{ $}}
9290
; CHECK-NEXT: bb.1.cmpxchg.start:
9391
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
9492
; CHECK-NEXT: liveins: $w1, $w2, $x0
@@ -127,7 +125,6 @@ define i64 @val_compare_and_swap_64(ptr %p, i64 %cmp, i64 %new) {
127125
; CHECK-NEXT: successors: %bb.1(0x80000000)
128126
; CHECK-NEXT: liveins: $x0, $x1, $x2
129127
; CHECK-NEXT: {{ $}}
130-
; CHECK-NEXT: {{ $}}
131128
; CHECK-NEXT: bb.1.cmpxchg.start:
132129
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
133130
; CHECK-NEXT: liveins: $x0, $x1, $x2
@@ -166,7 +163,6 @@ define i64 @val_compare_and_swap_64_monotonic_seqcst(ptr %p, i64 %cmp, i64 %new)
166163
; CHECK-NEXT: successors: %bb.1(0x80000000)
167164
; CHECK-NEXT: liveins: $x0, $x1, $x2
168165
; CHECK-NEXT: {{ $}}
169-
; CHECK-NEXT: {{ $}}
170166
; CHECK-NEXT: bb.1.cmpxchg.start:
171167
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
172168
; CHECK-NEXT: liveins: $x0, $x1, $x2
@@ -205,7 +201,6 @@ define i64 @val_compare_and_swap_64_release_acquire(ptr %p, i64 %cmp, i64 %new)
205201
; CHECK-NEXT: successors: %bb.1(0x80000000)
206202
; CHECK-NEXT: liveins: $x0, $x1, $x2
207203
; CHECK-NEXT: {{ $}}
208-
; CHECK-NEXT: {{ $}}
209204
; CHECK-NEXT: bb.1.cmpxchg.start:
210205
; CHECK-NEXT: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
211206
; CHECK-NEXT: liveins: $x0, $x1, $x2
@@ -244,7 +239,6 @@ define i32 @fetch_and_nand(ptr %p) {
244239
; CHECK-NEXT: successors: %bb.1(0x80000000)
245240
; CHECK-NEXT: liveins: $x0
246241
; CHECK-NEXT: {{ $}}
247-
; CHECK-NEXT: {{ $}}
248242
; CHECK-NEXT: bb.1.atomicrmw.start:
249243
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
250244
; CHECK-NEXT: liveins: $x0
@@ -270,7 +264,6 @@ define i64 @fetch_and_nand_64(ptr %p) {
270264
; CHECK-NEXT: successors: %bb.1(0x80000000)
271265
; CHECK-NEXT: liveins: $x0
272266
; CHECK-NEXT: {{ $}}
273-
; CHECK-NEXT: {{ $}}
274267
; CHECK-NEXT: bb.1.atomicrmw.start:
275268
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
276269
; CHECK-NEXT: liveins: $x0
@@ -322,7 +315,6 @@ define i64 @fetch_and_or_64(ptr %p) {
322315
; CHECK-NEXT: successors: %bb.1(0x80000000)
323316
; CHECK-NEXT: liveins: $x0
324317
; CHECK-NEXT: {{ $}}
325-
; CHECK-NEXT: {{ $}}
326318
; CHECK-NEXT: bb.1.atomicrmw.start:
327319
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
328320
; CHECK-NEXT: liveins: $x0
@@ -730,7 +722,6 @@ define i8 @atomicrmw_add_i8(ptr %ptr, i8 %rhs) {
730722
; CHECK-NEXT: successors: %bb.1(0x80000000)
731723
; CHECK-NEXT: liveins: $w1, $x0
732724
; CHECK-NEXT: {{ $}}
733-
; CHECK-NEXT: {{ $}}
734725
; CHECK-NEXT: bb.1.atomicrmw.start:
735726
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
736727
; CHECK-NEXT: liveins: $w1, $x0
@@ -780,7 +771,6 @@ define i8 @atomicrmw_sub_i8(ptr %ptr, i8 %rhs) {
780771
; CHECK-NEXT: successors: %bb.1(0x80000000)
781772
; CHECK-NEXT: liveins: $w1, $x0
782773
; CHECK-NEXT: {{ $}}
783-
; CHECK-NEXT: {{ $}}
784774
; CHECK-NEXT: bb.1.atomicrmw.start:
785775
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
786776
; CHECK-NEXT: liveins: $w1, $x0
@@ -805,7 +795,6 @@ define i8 @atomicrmw_and_i8(ptr %ptr, i8 %rhs) {
805795
; CHECK-NEXT: successors: %bb.1(0x80000000)
806796
; CHECK-NEXT: liveins: $w1, $x0
807797
; CHECK-NEXT: {{ $}}
808-
; CHECK-NEXT: {{ $}}
809798
; CHECK-NEXT: bb.1.atomicrmw.start:
810799
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
811800
; CHECK-NEXT: liveins: $w1, $x0
@@ -830,7 +819,6 @@ define i8 @atomicrmw_or_i8(ptr %ptr, i8 %rhs) {
830819
; CHECK-NEXT: successors: %bb.1(0x80000000)
831820
; CHECK-NEXT: liveins: $w1, $x0
832821
; CHECK-NEXT: {{ $}}
833-
; CHECK-NEXT: {{ $}}
834822
; CHECK-NEXT: bb.1.atomicrmw.start:
835823
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
836824
; CHECK-NEXT: liveins: $w1, $x0
@@ -855,7 +843,6 @@ define i8 @atomicrmw_xor_i8(ptr %ptr, i8 %rhs) {
855843
; CHECK-NEXT: successors: %bb.1(0x80000000)
856844
; CHECK-NEXT: liveins: $w1, $x0
857845
; CHECK-NEXT: {{ $}}
858-
; CHECK-NEXT: {{ $}}
859846
; CHECK-NEXT: bb.1.atomicrmw.start:
860847
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
861848
; CHECK-NEXT: liveins: $w1, $x0
@@ -880,7 +867,6 @@ define i8 @atomicrmw_min_i8(ptr %ptr, i8 %rhs) {
880867
; CHECK-NEXT: successors: %bb.1(0x80000000)
881868
; CHECK-NEXT: liveins: $w1, $x0
882869
; CHECK-NEXT: {{ $}}
883-
; CHECK-NEXT: {{ $}}
884870
; CHECK-NEXT: bb.1.atomicrmw.start:
885871
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
886872
; CHECK-NEXT: liveins: $w1, $x0
@@ -907,7 +893,6 @@ define i8 @atomicrmw_max_i8(ptr %ptr, i8 %rhs) {
907893
; CHECK-NEXT: successors: %bb.1(0x80000000)
908894
; CHECK-NEXT: liveins: $w1, $x0
909895
; CHECK-NEXT: {{ $}}
910-
; CHECK-NEXT: {{ $}}
911896
; CHECK-NEXT: bb.1.atomicrmw.start:
912897
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
913898
; CHECK-NEXT: liveins: $w1, $x0
@@ -990,7 +975,6 @@ define i16 @atomicrmw_add_i16(ptr %ptr, i16 %rhs) {
990975
; CHECK-NEXT: successors: %bb.1(0x80000000)
991976
; CHECK-NEXT: liveins: $w1, $x0
992977
; CHECK-NEXT: {{ $}}
993-
; CHECK-NEXT: {{ $}}
994978
; CHECK-NEXT: bb.1.atomicrmw.start:
995979
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
996980
; CHECK-NEXT: liveins: $w1, $x0
@@ -1040,7 +1024,6 @@ define i16 @atomicrmw_sub_i16(ptr %ptr, i16 %rhs) {
10401024
; CHECK-NEXT: successors: %bb.1(0x80000000)
10411025
; CHECK-NEXT: liveins: $w1, $x0
10421026
; CHECK-NEXT: {{ $}}
1043-
; CHECK-NEXT: {{ $}}
10441027
; CHECK-NEXT: bb.1.atomicrmw.start:
10451028
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
10461029
; CHECK-NEXT: liveins: $w1, $x0
@@ -1065,7 +1048,6 @@ define i16 @atomicrmw_and_i16(ptr %ptr, i16 %rhs) {
10651048
; CHECK-NEXT: successors: %bb.1(0x80000000)
10661049
; CHECK-NEXT: liveins: $w1, $x0
10671050
; CHECK-NEXT: {{ $}}
1068-
; CHECK-NEXT: {{ $}}
10691051
; CHECK-NEXT: bb.1.atomicrmw.start:
10701052
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
10711053
; CHECK-NEXT: liveins: $w1, $x0
@@ -1090,7 +1072,6 @@ define i16 @atomicrmw_or_i16(ptr %ptr, i16 %rhs) {
10901072
; CHECK-NEXT: successors: %bb.1(0x80000000)
10911073
; CHECK-NEXT: liveins: $w1, $x0
10921074
; CHECK-NEXT: {{ $}}
1093-
; CHECK-NEXT: {{ $}}
10941075
; CHECK-NEXT: bb.1.atomicrmw.start:
10951076
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
10961077
; CHECK-NEXT: liveins: $w1, $x0
@@ -1115,7 +1096,6 @@ define i16 @atomicrmw_xor_i16(ptr %ptr, i16 %rhs) {
11151096
; CHECK-NEXT: successors: %bb.1(0x80000000)
11161097
; CHECK-NEXT: liveins: $w1, $x0
11171098
; CHECK-NEXT: {{ $}}
1118-
; CHECK-NEXT: {{ $}}
11191099
; CHECK-NEXT: bb.1.atomicrmw.start:
11201100
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
11211101
; CHECK-NEXT: liveins: $w1, $x0
@@ -1140,7 +1120,6 @@ define i16 @atomicrmw_min_i16(ptr %ptr, i16 %rhs) {
11401120
; CHECK-NEXT: successors: %bb.1(0x80000000)
11411121
; CHECK-NEXT: liveins: $w1, $x0
11421122
; CHECK-NEXT: {{ $}}
1143-
; CHECK-NEXT: {{ $}}
11441123
; CHECK-NEXT: bb.1.atomicrmw.start:
11451124
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
11461125
; CHECK-NEXT: liveins: $w1, $x0
@@ -1167,7 +1146,6 @@ define i16 @atomicrmw_max_i16(ptr %ptr, i16 %rhs) {
11671146
; CHECK-NEXT: successors: %bb.1(0x80000000)
11681147
; CHECK-NEXT: liveins: $w1, $x0
11691148
; CHECK-NEXT: {{ $}}
1170-
; CHECK-NEXT: {{ $}}
11711149
; CHECK-NEXT: bb.1.atomicrmw.start:
11721150
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
11731151
; CHECK-NEXT: liveins: $w1, $x0

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir

-1
Original file line numberDiff line numberDiff line change
@@ -125,7 +125,6 @@ body: |
125125
; CHECK-NEXT: bb.1:
126126
; CHECK-NEXT: successors: %bb.2(0x80000000)
127127
; CHECK-NEXT: {{ $}}
128-
; CHECK-NEXT: {{ $}}
129128
; CHECK-NEXT: bb.2:
130129
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(p0) = G_PHI [[COPY]](p0), %bb.0, [[COPY1]](p0), %bb.1
131130
; CHECK-NEXT: $x0 = COPY [[PHI]](p0)

‎llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir

-1
Original file line numberDiff line numberDiff line change
@@ -158,7 +158,6 @@ body: |
158158
; CHECK-NEXT: bb.1:
159159
; CHECK-NEXT: successors: %bb.2(0x80000000)
160160
; CHECK-NEXT: {{ $}}
161-
; CHECK-NEXT: {{ $}}
162161
; CHECK-NEXT: bb.2:
163162
; CHECK-NEXT: %phi:gpr32 = PHI %copy1, %bb.0, %copy2, %bb.1
164163
; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %phi, 0

‎llvm/test/CodeGen/AArch64/GlobalISel/select-unreachable-blocks.mir

-1
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,6 @@ body: |
2323
; CHECK-NEXT: bb.1:
2424
; CHECK-NEXT: successors: %bb.2(0x80000000)
2525
; CHECK-NEXT: {{ $}}
26-
; CHECK-NEXT: {{ $}}
2726
; CHECK-NEXT: bb.2:
2827
; CHECK-NEXT: successors: %bb.3(0x80000000)
2928
; CHECK-NEXT: {{ $}}

‎llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll

-2
Original file line numberDiff line numberDiff line change
@@ -174,7 +174,6 @@ define i32 @dont_split3() {
174174
; CHECK-NEXT: bb.1.x:
175175
; CHECK-NEXT: successors: %bb.2(0x80000000)
176176
; CHECK-NEXT: {{ $}}
177-
; CHECK-NEXT: {{ $}}
178177
; CHECK-NEXT: bb.2.v (machine-block-address-taken, inlineasm-br-indirect-target):
179178
; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 42
180179
; CHECK-NEXT: $w0 = COPY [[MOVi32imm]]
@@ -424,7 +423,6 @@ define i32 @split_me3() {
424423
; CHECK-NEXT: bb.2.y:
425424
; CHECK-NEXT: successors: %bb.3(0x80000000)
426425
; CHECK-NEXT: {{ $}}
427-
; CHECK-NEXT: {{ $}}
428426
; CHECK-NEXT: bb.3.out:
429427
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY1]], %bb.1, [[COPY]], %bb.2
430428
; CHECK-NEXT: $w0 = COPY [[PHI]]

‎llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir

-1
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,6 @@ body: |
3232
; CHECK-NEXT: bb.1:
3333
; CHECK-NEXT: successors: %bb.2(0x80000000)
3434
; CHECK-NEXT: {{ $}}
35-
; CHECK-NEXT: {{ $}}
3635
; CHECK-NEXT: bb.2:
3736
; CHECK-NEXT: successors: %bb.3(0x0fbefbf0), %bb.4(0x70410410)
3837
; CHECK-NEXT: {{ $}}

‎llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir

-1
Original file line numberDiff line numberDiff line change
@@ -371,7 +371,6 @@ body: |
371371
; CHECK-NEXT: successors: %bb.8(0x80000000)
372372
; CHECK-NEXT: liveins: $fp, $w23, $w24, $x10, $x19, $x20, $x22, $x25, $x26, $x27
373373
; CHECK-NEXT: {{ $}}
374-
; CHECK-NEXT: {{ $}}
375374
; CHECK-NEXT: bb.8.bb79:
376375
; CHECK-NEXT: successors: %bb.9(0x04000000), %bb.8(0x7c000000)
377376
; CHECK-NEXT: liveins: $fp, $w23, $w24, $x10, $x19, $x20, $x22, $x25, $x26, $x27

‎llvm/test/CodeGen/AArch64/tail-dup-redundant-phi.mir

-2
Original file line numberDiff line numberDiff line change
@@ -252,7 +252,6 @@ body: |
252252
; CHECK-NEXT: bb.7.bb24:
253253
; CHECK-NEXT: successors: %bb.8(0x80000000)
254254
; CHECK-NEXT: {{ $}}
255-
; CHECK-NEXT: {{ $}}
256255
; CHECK-NEXT: bb.8.bb25:
257256
; CHECK-NEXT: successors: %bb.18(0x30000000), %bb.14(0x50000000)
258257
; CHECK-NEXT: {{ $}}
@@ -298,7 +297,6 @@ body: |
298297
; CHECK-NEXT: bb.11.bb35:
299298
; CHECK-NEXT: successors:
300299
; CHECK-NEXT: {{ $}}
301-
; CHECK-NEXT: {{ $}}
302300
; CHECK-NEXT: bb.13.bb40:
303301
; CHECK-NEXT: successors:
304302
; CHECK-NEXT: {{ $}}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll

-4
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,6 @@ define amdgpu_kernel void @return_type_is_too_big_vector() {
2020
; CHECK: bb.0:
2121
; CHECK-NEXT: successors: %bb.1(0x80000000)
2222
; CHECK-NEXT: {{ $}}
23-
; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1 (%ir-block.0):
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; CHECK-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $sgpr8_sgpr9_sgpr10_sgpr11_sgpr12
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%sgpr = call <4 x i32> asm sideeffect "; def $0", "={s[8:12]}" ()
@@ -40,7 +39,6 @@ define i64 @return_type_is_too_big_scalar() {
4039
; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
43-
; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1 (%ir-block.0):
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; CHECK-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $vgpr8
4644
%reg = call i64 asm sideeffect "; def $0", "={v8}" ()
@@ -64,7 +62,6 @@ define ptr addrspace(1) @return_type_is_too_big_pointer() {
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
67-
; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1 (%ir-block.0):
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; CHECK-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $vgpr8
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%reg = call ptr addrspace(1) asm sideeffect "; def $0", "={v8}" ()
@@ -76,7 +73,6 @@ define ptr addrspace(3) @return_type_is_too_small_pointer() {
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
79-
; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1 (%ir-block.0):
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; CHECK-NEXT: INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $vgpr8_vgpr9
8278
%reg = call ptr addrspace(3) asm sideeffect "; def $0", "={v[8:9]}" ()

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir

-1
Original file line numberDiff line numberDiff line change
@@ -89,7 +89,6 @@ body: |
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.2(0x80000000)
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; GCN-NEXT: {{ $}}
92-
; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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bb.0:
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liveins: $sgpr0, $sgpr1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir

-2
Original file line numberDiff line numberDiff line change
@@ -523,7 +523,6 @@ body: |
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; WAVE64-NEXT: bb.1:
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; WAVE64-NEXT: successors: %bb.2(0x80000000)
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; WAVE64-NEXT: {{ $}}
526-
; WAVE64-NEXT: {{ $}}
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; WAVE64-NEXT: bb.2:
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;
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; WAVE32-LABEL: name: zext_sgpr_s1_to_sgpr_s32
@@ -539,7 +538,6 @@ body: |
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; WAVE32-NEXT: bb.1:
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; WAVE32-NEXT: successors: %bb.2(0x80000000)
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; WAVE32-NEXT: {{ $}}
542-
; WAVE32-NEXT: {{ $}}
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; WAVE32-NEXT: bb.2:
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bb.0:
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%0:sgpr(s1) = G_CONSTANT i1 true

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