Make sure all the bitcasts are handled

Author: ThomasRaoux

llvm/lib/Target/NVPTX/NVPTXInstrInfo.td

@@ -2943,15 +2943,13 @@ def BITCONVERT_32_F2I : F_BITCONVERT<"32", f32, i32>;
 def BITCONVERT_64_I2F : F_BITCONVERT<"64", i64, f64>;
 def BITCONVERT_64_F2I : F_BITCONVERT<"64", f64, i64>;
 
-foreach vt = [v2f16, v2bf16] in {
+foreach vt = [v2f16, v2bf16, v2i16] in {
 def: Pat<(vt (bitconvert (i32 UInt32Const:$a))),
          (IMOVB32ri UInt32Const:$a)>;
-def: Pat<(vt (bitconvert (i32 Int32Regs:$a))),
-         (ProxyRegI32 Int32Regs:$a)>;
-def: Pat<(i32 (bitconvert (vt Int32Regs:$a))),
-         (ProxyRegI32 Int32Regs:$a)>;
 def: Pat<(vt (bitconvert (f32 Float32Regs:$a))),
          (BITCONVERT_32_F2I Float32Regs:$a)>;
+def: Pat<(f32 (bitconvert (vt Int32Regs:$a))),
+         (BITCONVERT_32_I2F Int32Regs:$a)>;
 }
 foreach vt = [f16, bf16] in {
 def: Pat<(vt (bitconvert (i16 UInt16Const:$a))),
@@ -2962,10 +2960,14 @@ def: Pat<(i16 (bitconvert (vt Int16Regs:$a))),
          (ProxyRegI16 Int16Regs:$a)>;
 }
 
-def: Pat<(v2i16 (bitconvert (i32 Int32Regs:$a))),
-         (ProxyRegI32 Int32Regs:$a)>;
-def: Pat<(i32 (bitconvert (v2i16 Int32Regs:$a))),
-         (ProxyRegI32 Int32Regs:$a)>;
+foreach ta = [v2f16, v2bf16, v2i16, i32] in {
+  foreach tb = [v2f16, v2bf16, v2i16, i32] in {
+    if !ne(ta, tb) then {
+      def: Pat<(ta (bitconvert (tb Int32Regs:$a))),
+             (ProxyRegI32 Int32Regs:$a)>;
+    }
+  }
+}
 
 // NOTE: pred->fp are currently sub-optimal due to an issue in TableGen where
 // we cannot specify floating-point literals in isel patterns.  Therefore, we

llvm/test/CodeGen/NVPTX/i16x2-instructions.ll

@@ -20,7 +20,7 @@
 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
 
 ; COMMON-LABEL: test_ret_const(
-; COMMON:     mov.u32         [[R:%r[0-9+]]], 131073;
+; COMMON:     mov.b32         [[R:%r[0-9+]]], 131073;
 ; COMMON:     st.param.b32    [func_retval0+0], [[R]];
 ; COMMON-NEXT: ret;
 define <2 x i16> @test_ret_const() #0 {
@@ -86,7 +86,7 @@ define <2 x i16> @test_add(<2 x i16> %a, <2 x i16> %b) #0 {
 ; COMMON-LABEL: test_add_imm_0(
 ; COMMON-DAG:  ld.param.u32    [[A:%r[0-9]+]], [test_add_imm_0_param_0];
 ;
-; I16x2:        mov.u32        [[I:%r[0-9+]]], 131073;
+; I16x2:        mov.b32        [[I:%r[0-9+]]], 131073;
 ; I16x2:        add.s16x2      [[R:%r[0-9]+]], [[A]], [[I]];
 ;
 ;	NO-I16x2-DAG: mov.b32 	{[[RS0:%rs[0-9]+]], [[RS1:%rs[0-9]+]]}, [[A]];
@@ -104,7 +104,7 @@ define <2 x i16> @test_add_imm_0(<2 x i16> %a) #0 {
 ; COMMON-LABEL: test_add_imm_1(
 ; COMMON-DAG:  ld.param.u32    [[B:%r[0-9]+]], [test_add_imm_1_param_0];
 ;
-; I16x2:        mov.u32        [[I:%r[0-9+]]], 131073;
+; I16x2:        mov.b32        [[I:%r[0-9+]]], 131073;
 ; I16x2:        add.s16x2      [[R:%r[0-9]+]], [[A]], [[I]];
 ;
 ;	NO-I16x2-DAG: mov.b32 	{[[RS0:%rs[0-9]+]], [[RS1:%rs[0-9]+]]}, [[A]];
@@ -497,6 +497,20 @@ define i32 @test_bitcast_2xi16_to_i32(<2 x i16> %a) #0 {
   ret i32 %r
 }
 
+; COMMON-LABEL: test_bitcast_2xi16_to_2xhalf(
+; COMMON: ld.param.u16 	[[RS1:%rs[0-9]+]], [test_bitcast_2xi16_to_2xhalf_param_0];
+; COMMON:	mov.u16 	[[RS2:%rs[0-9]+]], 5;
+; COMMON:	mov.b32 	[[R:%r[0-9]+]], {[[RS1]], [[RS2]]};
+; COMMON: st.param.b32 	[func_retval0+0], [[R]];
+; COMMON: ret;
+define <2 x half> @test_bitcast_2xi16_to_2xhalf(i16 %a) #0 {
+  %ins.0 = insertelement <2 x i16> undef, i16 %a, i32 0
+  %ins.1 = insertelement <2 x i16> %ins.0, i16 5, i32 1
+  %r = bitcast <2 x i16> %ins.1 to <2 x half>
+  ret <2 x half> %r
+}
+
+
 ; COMMON-LABEL: test_shufflevector(
 ; COMMON:	ld.param.u32 	[[R:%r[0-9]+]], [test_shufflevector_param_0];
 ; COMMON:	mov.b32 	{[[RS0:%rs[0-9]+]], [[RS1:%rs[0-9]+]]}, [[R]];