ARM instruction selection failure when -promote-elements=true and -mattr=+neon

[llvmbot]

Bugzilla Link	11319
Resolution	FIXED
Resolved on	Nov 10, 2011 21:17
Version	trunk
OS	Linux
Attachments	The test cases to reproduce the bug.
Reporter	LLVM Bugzilla Contributor
CC	@efriedma-quic,@stephenhines

Extended Description

When we enable ARM NEON (-mattr=+neon) during the code generation, llc will return either instruction selection failure or assertion failure on APInt bit width in some circumstance (see the attached test cases).

After further inspection, we found that only if both of the following flags are enabled will the bug occur:

(a) -mattr=+neon : This flag enables the code generation for ARM NEON instruction.

(b) -promote-elements=true : This flag enables some vector type to vector type promotion during the legalization process. This flag has been enabled by default since revision 142152.

PROCEDURE TO REPRODUCE:

1. Fetch and build the LLVM.

2. Download the attached test case, extract the files, and place them in /test/CodeGen/ARM

3. Run "make check". The expected behavior is that no additional unexpected test failure is discovered. But there will be 6 additional test failures after adding the attached test cases.

[efriedma-quic]

Potential fix
I think this is the right approach...

[efriedma-quic]

Nadav, does the attached patch look correct?

[llvmbot]

Eli, Yes. This patch looks good to me.

[efriedma-quic]

r144057.

[stephenhines]

2011-11-05-NeonCallReturnVector.ll from the attached test cases is still failing with the following output:

$ llc -march=arm -mattr=+neon < 2011-11-05-NeonCallReturnVector.ll
.syntax unified
.eabi_attribute 6, 2
.eabi_attribute 8, 1
.eabi_attribute 9, 1
.fpu neon
.eabi_attribute 10, 3
.eabi_attribute 12, 1
.eabi_attribute 20, 1
.eabi_attribute 21, 1
.eabi_attribute 23, 3
.eabi_attribute 24, 1
.eabi_attribute 25, 1
.file ""
llc: /srhines-dt/srhines/llvm_git/llvm/include/llvm/ADT/APInt.h:847: bool llvm::APInt::operator==(const llvm::APInt &) const: Assertion `BitWidth == RHS.BitWidth && "Comparison requires equal bit widths"' failed.
0 llc 0x08a16f5b
Stack dump:
0. Program arguments: llc -march=arm -mattr=+neon

1. Running pass 'Function Pass Manager' on module ''.
2. Running pass 'ARM Instruction Selection' on function '@test_neon_call_return_v2i8'
   Aborted

[efriedma-quic]

r144216.

[stephenhines]

Sorry that I wasn't more specific with my last comment. The remaining 4 test cases still fail as well (for slightly different reasons). The logs from running llc are below:

2011-11-05-NeonVolatile_v216.ll
2011-11-05-NeonVolatile_v2i8.ll
2011-11-05-NeonVolatile_v3i8.ll
2011-11-05-NeonVolatile_v4i8.ll

2011-11-05-NeonVolatile_v216.ll
LLVM ERROR: Cannot select: 0xa817b00: v2i32 = sign_extend_inreg 0xa81b078, 0xa8179f0 [ID=43]
0xa81b078: v2i32 = bitcast 0xa81aff0 [ID=40]
0xa81aff0: v2f32 = ARMISD::BUILD_VECTOR 0xa81a5d8, 0xa81af68 [ID=37]
0xa81a5d8: f32 = bitcast 0xa817e30 [ID=34]
0xa817e30: i32,ch = load 0xa817d20, 0xa81b430, 0xa817528<Volatile LD2@src2, anyext from i16> [ID=31]
0xa81b430: i32,ch = load 0xa7feec4, 0xa81b3a8, 0xa817528<LD4[ConstantPool]> [ID=19]
0xa81b3a8: i32 = ARMISD::Wrapper 0xa8177d0 [ID=16]
0xa8177d0: i32 = TargetConstantPool<@src2 = global <2 x i16> <i16 1, i16 1>

0 [ID=11]
0xa817528: i32 = undef [ORD=1] [ID=1]
0xa817528: i32 = undef [ORD=1] [ID=1]
0xa81af68: f32 = bitcast 0xa817f40 [ID=33]
0xa817f40: i32,ch = load 0xa817d20, 0xa817eb8, 0xa817528<Volatile LD2@src2(align=4)+2, anyext from i16> [ID=30]
0xa817eb8: i32 = add 0xa81b430, 0xa8176c0 [ID=22]
0xa81b430: i32,ch = load 0xa7feec4, 0xa81b3a8, 0xa817528<LD4[ConstantPool]> [ID=19]
0xa81b3a8: i32 = ARMISD::Wrapper 0xa8177d0 [ID=16]
0xa8177d0: i32 = TargetConstantPool<@src2 = global <2 x i16> <i16 1, i16 1>
0 [ID=11]
0xa817528: i32 = undef [ORD=1] [ID=1]
0xa8176c0: i32 = Constant<2> [ID=3]
0xa817528: i32 = undef [ORD=1] [ID=1]

2011-11-05-Ne

[efriedma-quic]

r144361.