From 1605d25d68378ccd618a1bc2df708585cd8a2170 Mon Sep 17 00:00:00 2001 From: Natalie Chouinard Date: Mon, 18 Sep 2023 18:42:35 +0000 Subject: [PATCH] [SPIR-V] Fix 64-bit integer literal printing Previously, the SPIR-V instruction printer was always printing the first operand of an OpConstant's variable value as one of the fixed operands. This is incorrect for 64-bit values, where the first operand is actually the value's lower word and should be combined with the following higher order word before printing. This change fixes that issue by waiting to print the last fixed operand of OpConstant instructions until the variadic operands are ready to be printed, then using NumFixedOps - 1 as the starting operand index for the variable value operands. Depends on D156049 --- llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp | 4 +++- llvm/lib/Target/SPIRV/SPIRVInstrInfo.td | 4 ++-- llvm/test/CodeGen/SPIRV/atomicrmw.ll | 4 ++-- llvm/test/CodeGen/SPIRV/constant/local-integers-constants.ll | 4 ++-- llvm/test/CodeGen/SPIRV/lshr-constexpr.ll | 2 +- llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll | 4 ++-- 6 files changed, 12 insertions(+), 10 deletions(-) diff --git a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp index a1e90cd104a97..e472f7bcbaa50 100644 --- a/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp +++ b/llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVInstPrinter.cpp @@ -169,7 +169,9 @@ void SPIRVInstPrinter::printInst(const MCInst *MI, uint64_t Address, } case SPIRV::OpConstantI: case SPIRV::OpConstantF: - printOpConstantVarOps(MI, NumFixedOps, OS); + // The last fixed operand along with any variadic operands that follow + // are part of the variable value. + printOpConstantVarOps(MI, NumFixedOps - 1, OS); break; default: printRemainingVariableOps(MI, NumFixedOps, OS); diff --git a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td index 44b5536becf7f..5f3bc30591fa5 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td +++ b/llvm/lib/Target/SPIRV/SPIRVInstrInfo.td @@ -217,9 +217,9 @@ def ConstPseudoNull: IntImmLeaf; multiclass IntFPImm opCode, string name> { def I: Op; + "$dst = "#name#" $type", [(set ID:$dst, (assigntype PseudoConstI:$src, TYPE:$type))]>; def F: Op; + "$dst = "#name#" $type", [(set ID:$dst, (assigntype PseudoConstF:$src, TYPE:$type))]>; } def OpConstantTrue: Op<41, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantTrue $src_ty", diff --git a/llvm/test/CodeGen/SPIRV/atomicrmw.ll b/llvm/test/CodeGen/SPIRV/atomicrmw.ll index de192d5bd422d..dc964e7498445 100644 --- a/llvm/test/CodeGen/SPIRV/atomicrmw.ll +++ b/llvm/test/CodeGen/SPIRV/atomicrmw.ll @@ -1,10 +1,10 @@ ; RUN: llc -O0 -opaque-pointers=0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s ; CHECK: %[[#Int:]] = OpTypeInt 32 0 -; CHECK-DAG: %[[#Scope_Device:]] = OpConstant %[[#Int]] 1 {{$}} +; CHECK-DAG: %[[#Scope_Device:]] = OpConstant %[[#Int]] 1{{$}} ; CHECK-DAG: %[[#MemSem_Relaxed:]] = OpConstant %[[#Int]] 0 ; CHECK-DAG: %[[#MemSem_Acquire:]] = OpConstant %[[#Int]] 2 -; CHECK-DAG: %[[#MemSem_Release:]] = OpConstant %[[#Int]] 4 {{$}} +; CHECK-DAG: %[[#MemSem_Release:]] = OpConstant %[[#Int]] 4{{$}} ; CHECK-DAG: %[[#MemSem_AcquireRelease:]] = OpConstant %[[#Int]] 8 ; CHECK-DAG: %[[#MemSem_SequentiallyConsistent:]] = OpConstant %[[#Int]] 16 ; CHECK-DAG: %[[#Value:]] = OpConstant %[[#Int]] 42 diff --git a/llvm/test/CodeGen/SPIRV/constant/local-integers-constants.ll b/llvm/test/CodeGen/SPIRV/constant/local-integers-constants.ll index 9660ba446cfca..5cfc0d2e9dc8f 100644 --- a/llvm/test/CodeGen/SPIRV/constant/local-integers-constants.ll +++ b/llvm/test/CodeGen/SPIRV/constant/local-integers-constants.ll @@ -44,8 +44,8 @@ define i64 @getLargeConstantI64() { ; CHECK-DAG: %[[#CST_I8:]] = OpConstant %[[#I8]] 2 ; CHECK-DAG: %[[#CST_I16:]] = OpConstant %[[#I16]] 65478 ; CHECK-DAG: %[[#CST_I32:]] = OpConstant %[[#I32]] 42 -; CHECK-DAG: %[[#CST_I64:]] = OpConstant %[[#I64]] 123456789 0 -; CHECK-DAG: %[[#CST_LARGE_I64:]] = OpConstant %[[#I64]] 0 8 +; CHECK-DAG: %[[#CST_I64:]] = OpConstant %[[#I64]] 123456789 +; CHECK-DAG: %[[#CST_LARGE_I64:]] = OpConstant %[[#I64]] 34359738368 ; CHECK: %[[#GET_I8]] = OpFunction %[[#I8]] ; CHECK: OpReturnValue %[[#CST_I8]] diff --git a/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll b/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll index c435cb25ef5c2..44b11f3ddb273 100644 --- a/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll +++ b/llvm/test/CodeGen/SPIRV/lshr-constexpr.ll @@ -5,7 +5,7 @@ ; CHECK-SPIRV: %[[#type_vec:]] = OpTypeVector %[[#type_int32]] 2 ; CHECK-SPIRV: %[[#const1:]] = OpConstant %[[#type_int32]] 1 ; CHECK-SPIRV: %[[#vec_const:]] = OpConstantComposite %[[#type_vec]] %[[#const1]] %[[#const1]] -; CHECK-SPIRV: %[[#const32:]] = OpConstant %[[#type_int64]] 32 0 +; CHECK-SPIRV: %[[#const32:]] = OpConstant %[[#type_int64]] 32 ; CHECK-SPIRV: %[[#bitcast_res:]] = OpBitcast %[[#type_int64]] %[[#vec_const]] ; CHECK-SPIRV: %[[#shift_res:]] = OpShiftRightLogical %[[#type_int64]] %[[#bitcast_res]] %[[#const32]] diff --git a/llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll b/llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll index 75997a37bafff..2fe0dc91e7b4c 100644 --- a/llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll +++ b/llvm/test/CodeGen/SPIRV/uitofp-with-bool.ll @@ -41,10 +41,10 @@ ; SPV-DAG: %[[#mone_16:]] = OpConstant %[[#int_16]] 65535 ; SPV-DAG: %[[#mone_32:]] = OpConstant %[[#int_32]] 4294967295 ; SPV-DAG: %[[#zero_64:]] = OpConstantNull %[[#int_64]] -; SPV-DAG: %[[#mone_64:]] = OpConstant %[[#int_64]] 4294967295 4294967295 +; SPV-DAG: %[[#mone_64:]] = OpConstant %[[#int_64]] 18446744073709551615 ; SPV-DAG: %[[#one_8:]] = OpConstant %[[#int_8]] 1 ; SPV-DAG: %[[#one_16:]] = OpConstant %[[#int_16]] 1 -; SPV-DAG: %[[#one_64:]] = OpConstant %[[#int_64]] 1 0 +; SPV-DAG: %[[#one_64:]] = OpConstant %[[#int_64]] 1 ; SPV-DAG: %[[#void:]] = OpTypeVoid ; SPV-DAG: %[[#float:]] = OpTypeFloat 32 ; SPV-DAG: %[[#bool:]] = OpTypeBool