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[GISel] Make assignValueToReg take CCValAssign by const reference. #70086

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Merged
merged 1 commit into from
Oct 24, 2023
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[GISel] Make assignValueToReg take CCValAssign by const reference. #70086

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7 changes: 4 additions & 3 deletions llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
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Original file line number Diff line number Diff line change
Expand Up @@ -268,7 +268,7 @@ class CallLowering {
/// handle the appropriate COPY (either to or from) and mark any
/// relevant uses/defines as needed.
virtual void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) = 0;
const CCValAssign &VA) = 0;

/// The specified value has been assigned to a stack
/// location. Load or store it there, with appropriate extension
Expand Down Expand Up @@ -323,11 +323,12 @@ class CallLowering {

/// Insert G_ASSERT_ZEXT/G_ASSERT_SEXT or other hint instruction based on \p
/// VA, returning the new register if a hint was inserted.
Register buildExtensionHint(CCValAssign &VA, Register SrcReg, LLT NarrowTy);
Register buildExtensionHint(const CCValAssign &VA, Register SrcReg,
LLT NarrowTy);

/// Provides a default implementation for argument handling.
void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override;
const CCValAssign &VA) override;
};

/// Base class for ValueHandlers used for arguments passed to a function call,
Expand Down
10 changes: 4 additions & 6 deletions llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
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Expand Up @@ -1184,9 +1184,8 @@ Register CallLowering::ValueHandler::extendRegister(Register ValReg,

void CallLowering::ValueAssigner::anchor() {}

Register CallLowering::IncomingValueHandler::buildExtensionHint(CCValAssign &VA,
Register SrcReg,
LLT NarrowTy) {
Register CallLowering::IncomingValueHandler::buildExtensionHint(
const CCValAssign &VA, Register SrcReg, LLT NarrowTy) {
switch (VA.getLocInfo()) {
case CCValAssign::LocInfo::ZExt: {
return MIRBuilder
Expand Down Expand Up @@ -1226,9 +1225,8 @@ static bool isCopyCompatibleType(LLT SrcTy, LLT DstTy) {
(DstTy.isPointer() && SrcTy.isScalar());
}

void CallLowering::IncomingValueHandler::assignValueToReg(Register ValVReg,
Register PhysReg,
CCValAssign VA) {
void CallLowering::IncomingValueHandler::assignValueToReg(
Register ValVReg, Register PhysReg, const CCValAssign &VA) {
const MVT LocVT = VA.getLocVT();
const LLT LocTy(LocVT);
const LLT RegTy = MRI.getType(ValVReg);
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
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Expand Up @@ -158,7 +158,7 @@ struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
}

void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override {
const CCValAssign &VA) override {
markPhysRegUsed(PhysReg);
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
}
Expand Down Expand Up @@ -284,7 +284,7 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
}

void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override {
const CCValAssign &VA) override {
MIB.addUse(PhysReg, RegState::Implicit);
Register ExtReg = extendRegister(ValVReg, VA);
MIRBuilder.buildCopy(PhysReg, ExtReg);
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
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Expand Up @@ -62,7 +62,7 @@ struct AMDGPUOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
}

void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override {
const CCValAssign &VA) override {
Register ExtReg = extendRegisterMin32(*this, ValVReg, VA);

// If this is a scalar return, insert a readfirstlane just in case the value
Expand Down Expand Up @@ -118,7 +118,7 @@ struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler {
}

void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override {
const CCValAssign &VA) override {
markPhysRegUsed(PhysReg);

if (VA.getLocVT().getSizeInBits() < 32) {
Expand Down Expand Up @@ -231,7 +231,7 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
}

void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override {
const CCValAssign &VA) override {
MIB.addUse(PhysReg, RegState::Implicit);
Register ExtReg = extendRegisterMin32(*this, ValVReg, VA);
MIRBuilder.buildCopy(PhysReg, ExtReg);
Expand Down
12 changes: 6 additions & 6 deletions llvm/lib/Target/ARM/ARMCallLowering.cpp
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Expand Up @@ -110,7 +110,7 @@ struct ARMOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
}

void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override {
const CCValAssign &VA) override {
assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");

Expand All @@ -136,14 +136,14 @@ struct ARMOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
std::function<void()> *Thunk) override {
assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");

CCValAssign VA = VAs[0];
const CCValAssign &VA = VAs[0];
assert(VA.needsCustom() && "Value doesn't need custom handling");

// Custom lowering for other types, such as f16, is currently not supported
if (VA.getValVT() != MVT::f64)
return 0;

CCValAssign NextVA = VAs[1];
const CCValAssign &NextVA = VAs[1];
assert(NextVA.needsCustom() && "Value doesn't need custom handling");
assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");

Expand Down Expand Up @@ -283,7 +283,7 @@ struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler {
}

void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override {
const CCValAssign &VA) override {
assert(VA.isRegLoc() && "Value shouldn't be assigned to reg");
assert(VA.getLocReg() == PhysReg && "Assigning to the wrong reg?");

Expand Down Expand Up @@ -312,14 +312,14 @@ struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler {
std::function<void()> *Thunk) override {
assert(Arg.Regs.size() == 1 && "Can't handle multple regs yet");

CCValAssign VA = VAs[0];
const CCValAssign &VA = VAs[0];
assert(VA.needsCustom() && "Value doesn't need custom handling");

// Custom lowering for other types, such as f16, is currently not supported
if (VA.getValVT() != MVT::f64)
return 0;

CCValAssign NextVA = VAs[1];
const CCValAssign &NextVA = VAs[1];
assert(NextVA.needsCustom() && "Value doesn't need custom handling");
assert(NextVA.getValVT() == MVT::f64 && "Unsupported type");

Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp
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Expand Up @@ -36,7 +36,7 @@ struct M68kOutgoingArgHandler : public CallLowering::OutgoingValueHandler {
STI(MIRBuilder.getMF().getSubtarget<M68kSubtarget>()) {}

void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override {
const CCValAssign &VA) override {
MIB.addUse(PhysReg, RegState::Implicit);
Register ExtReg = extendRegister(ValVReg, VA);
MIRBuilder.buildCopy(PhysReg, ExtReg);
Expand Down Expand Up @@ -127,7 +127,7 @@ bool M68kCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,

void M68kIncomingValueHandler::assignValueToReg(Register ValVReg,
Register PhysReg,
CCValAssign VA) {
const CCValAssign &VA) {
MIRBuilder.getMRI()->addLiveIn(PhysReg);
MIRBuilder.getMBB().addLiveIn(PhysReg);
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
Expand Down Expand Up @@ -160,7 +160,7 @@ Register M68kIncomingValueHandler::getStackAddress(uint64_t Size,
}

void CallReturnHandler::assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) {
const CCValAssign &VA) {
MIB.addDef(PhysReg, RegState::Implicit);
MIRBuilder.buildCopy(ValVReg, PhysReg);
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/M68k/GISel/M68kCallLowering.h
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Expand Up @@ -53,7 +53,7 @@ struct M68kIncomingValueHandler : public CallLowering::IncomingValueHandler {

private:
void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override;
const CCValAssign &VA) override;

void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
const MachinePointerInfo &MPO,
Expand All @@ -76,7 +76,7 @@ struct CallReturnHandler : public M68kIncomingValueHandler {

private:
void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override;
const CCValAssign &VA) override;

MachineInstrBuilder &MIB;
};
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/Mips/MipsCallLowering.cpp
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Expand Up @@ -93,7 +93,7 @@ class MipsIncomingValueHandler : public CallLowering::IncomingValueHandler {

private:
void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override;
const CCValAssign &VA) override;

Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO,
Expand Down Expand Up @@ -130,7 +130,7 @@ class CallReturnHandler : public MipsIncomingValueHandler {

void MipsIncomingValueHandler::assignValueToReg(Register ValVReg,
Register PhysReg,
CCValAssign VA) {
const CCValAssign &VA) {
markPhysRegUsed(PhysReg);
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
}
Expand Down Expand Up @@ -200,7 +200,7 @@ class MipsOutgoingValueHandler : public CallLowering::OutgoingValueHandler {

private:
void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override;
const CCValAssign &VA) override;

Register getStackAddress(uint64_t Size, int64_t Offset,
MachinePointerInfo &MPO,
Expand All @@ -219,7 +219,7 @@ class MipsOutgoingValueHandler : public CallLowering::OutgoingValueHandler {

void MipsOutgoingValueHandler::assignValueToReg(Register ValVReg,
Register PhysReg,
CCValAssign VA) {
const CCValAssign &VA) {
Register ExtReg = extendRegister(ValVReg, VA);
MIRBuilder.buildCopy(PhysReg, ExtReg);
MIB.addUse(PhysReg, RegState::Implicit);
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp
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Expand Up @@ -36,7 +36,7 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
: OutgoingValueHandler(MIRBuilder, MRI), MIB(MIB) {}

void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override;
const CCValAssign &VA) override;
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
const MachinePointerInfo &MPO,
const CCValAssign &VA) override;
Expand All @@ -49,7 +49,7 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
} // namespace

void OutgoingArgHandler::assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) {
const CCValAssign &VA) {
MIB.addUse(PhysReg, RegState::Implicit);
Register ExtReg = extendRegister(ValVReg, VA);
MIRBuilder.buildCopy(PhysReg, ExtReg);
Expand Down Expand Up @@ -144,7 +144,7 @@ bool PPCCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,

void PPCIncomingValueHandler::assignValueToReg(Register ValVReg,
Register PhysReg,
CCValAssign VA) {
const CCValAssign &VA) {
markPhysRegUsed(PhysReg);
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
}
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h
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Expand Up @@ -46,7 +46,7 @@ class PPCIncomingValueHandler : public CallLowering::IncomingValueHandler {

private:
void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override;
const CCValAssign &VA) override;

void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
const MachinePointerInfo &MPO,
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
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Expand Up @@ -93,7 +93,7 @@ struct RISCVOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
}

void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override {
const CCValAssign &VA) override {
Register ExtReg = extendRegister(ValVReg, VA);
MIRBuilder.buildCopy(PhysReg, ExtReg);
MIB.addUse(PhysReg, RegState::Implicit);
Expand Down Expand Up @@ -165,7 +165,7 @@ struct RISCVIncomingValueHandler : public CallLowering::IncomingValueHandler {
}

void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override {
const CCValAssign &VA) override {
markPhysRegUsed(PhysReg);
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
}
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/GISel/X86CallLowering.cpp
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Expand Up @@ -106,7 +106,7 @@ struct X86OutgoingValueHandler : public CallLowering::OutgoingValueHandler {
}

void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override {
const CCValAssign &VA) override {
MIB.addUse(PhysReg, RegState::Implicit);
Register ExtReg = extendRegister(ValVReg, VA);
MIRBuilder.buildCopy(PhysReg, ExtReg);
Expand Down Expand Up @@ -212,7 +212,7 @@ struct X86IncomingValueHandler : public CallLowering::IncomingValueHandler {
}

void assignValueToReg(Register ValVReg, Register PhysReg,
CCValAssign VA) override {
const CCValAssign &VA) override {
markPhysRegUsed(PhysReg);
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
}
Expand Down