failed to synthesize RTL with Yosys

[hyn0711]

I took an error when I run './syn_yosys.sh'

syn_yosys.sh ------------------------------

#!/bin/bash

set -e
set -o pipefail

error () {
echo >&2 "$@"
exit 1
}

teelog () {
tee "$LR_SYNTH_OUT_DIR/log/$1.log"
}

if [ ! -f syn_setup.sh ]; then
error "No syn_setup.sh file: see README.md for instructions"
fi

source syn_setup.sh

LR_DEP_SOURCES=(
"../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_buf.sv"
"../vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_flop.sv"

)

mkdir -p "$LR_SYNTH_OUT_DIR/generated"
mkdir -p "$LR_SYNTH_OUT_DIR/log"
mkdir -p "$LR_SYNTH_OUT_DIR/reports/timing"

for file in "${LR_DEP_SOURCES[@]}"; do
module=$(basename -s .sv "$file")

sv2v \
    --define=SYNTHESIS --define=YOSYS \
    -I../vendor/lowrisc_ip/ip/prim/rtl \
    "$file" \
    > "$LR_SYNTH_OUT_DIR"/generated/"${module}".v

done

for file in ../rtl/*.sv; do
module=$(basename -s .sv "$file")

if echo "$module" | grep -q '_pkg$'; then
continue
fi

sv2v
--define=SYNTHESIS --define=YOSYS
../rtl/*_pkg.sv
../vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv
../vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv
../vendor/lowrisc_ip/ip/prim/rtl/prim_lfsr.sv
../vendor/lowrisc_ip/ip/prim/rtl/prim_count.sv
../vendor/lowrisc_ip/ip/prim/rtl/prim_count_pkg.sv
-I../vendor/lowrisc_ip/ip/prim/rtl
-I../vendor/lowrisc_ip/dv/sv/dv_utils
"$file"
> "$LR_SYNTH_OUT_DIR"/generated/"${module}".v

sed -i 's/prim_buf/prim_generic_buf/g' "$LR_SYNTH_OUT_DIR"/generated/"${module}".v
sed -i 's/prim_flop/prim_generic_flop/g' "$LR_SYNTH_OUT_DIR"/generated/"${module}".v
done

rm -f "$LR_SYNTH_OUT_DIR"/generated/ibex_tracer.v

rm -f "$LR_SYNTH_OUT_DIR"/generated/ibex_register_file_ff.v
rm -f "$LR_SYNTH_OUT_DIR"/generated/ibex_register_file_fpga.v

yosys -c ./tcl/yosys_run_synth.tcl |& teelog syn || {
error "Failed to synthesize RTL with Yosys"
}

sta ./tcl/sta_run_reports.tcl |& teelog sta || {
error "Failed to run static timing analysis"
}

./translate_timing_rpts.sh

python/get_kge.py "$LR_SYNTH_CELL_LIBRARY_PATH" "$LR_SYNTH_OUT_DIR"/reports/area.rpt

---

I modified the code for yosys_run_synth.tcl
yosys "read_verilog -sv ./rtl/prim_clock_gating.v $lr_synth_out_dir/generated/*.v" (delete '-defer')

---

I got this error

1. Executing Liberty frontend.
   Imported 135 cell types from liberty file.

2. Executing Verilog-2005 frontend: ./rtl/prim_clock_gating.v
   Parsing SystemVerilog input from ./rtl/prim_clock_gating.v' to AST representation. Generating RTLIL representation for module \prim_clock_gating'.
   Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: syn_out/ibex_05_03_2025_20_43_12/generated/ibex_alu.v
   syn_out/ibex_05_03_2025_20_43_12/generated/ibex_alu.v:47: ERROR: Condition for generate if is not constant!
   Failed to synthesize RTL with Yosys

[marnovandermaas]

Thanks for trying this out. This script is experimental:

ibex/syn/README.md

Lines 1 to 3 in 6e466c1

	**This synthesis flow is experimental and under development, it does not produce
	tape-out quality netlists and area/timing numbers it generates are not
	representative of what would be achievable with a tape-out quality flow**

Also, it looks like the flow was updated 3 years ago. You could try running the script at an older revision:
https://github.com/lowRISC/ibex/tree/ea4e9383dbc6614e811ebe0b55cdb14779aee7ca
If you find any fix, I encourage you to open a PR so that we can update the flow.