Add initial VM skeleton

Author: xxuejie

Cargo.toml

@@ -4,3 +4,6 @@ version = "0.1.0"
 authors = ["Nervos Core Dev <dev@nervos.org>"]
 
 [dependencies]
+byteorder = "1"
+goblin = "0.0.17"
+

Makefile

@@ -0,0 +1,10 @@
+test:
+	RUSTFLAGS="--cfg ckb_test" cargo test --all -- --nocapture
+
+fmt:
+	cargo fmt --all -- --check
+
+clippy:
+	cargo clippy --all -- -D warnings -D clone_on_ref_ptr -D unused_extern_crates -D enum_glob_use
+
+.PHONY: test clippy fmt

clippy.toml

@@ -0,0 +1 @@
+single-char-binding-names-threshold = 4

rustfmt.toml

@@ -0,0 +1,5 @@
+max_width = 100
+tab_spaces = 4
+reorder_imports = true
+reorder_modules = true
+use_try_shorthand = true

src/decoder.rs

@@ -0,0 +1,38 @@
+use super::instructions::{rv32i, Instruction, InstructionFactory};
+use super::machine::Machine;
+use super::Error;
+
+pub struct Decoder {
+    factories: Vec<InstructionFactory>,
+}
+
+impl Decoder {
+    pub fn new() -> Decoder {
+        Decoder {
+            factories: Vec::new(),
+        }
+    }
+
+    pub fn add_instruction_factory(&mut self, factory: InstructionFactory) {
+        self.factories.push(factory);
+    }
+
+    pub fn decode(&self, machine: &Machine) -> Result<Instruction, Error> {
+        let mut instruction: u32 = u32::from(machine.memory.load16(machine.pc as usize)?);
+        if instruction & 0x3 == 0x3 {
+            instruction |= u32::from(machine.memory.load16(machine.pc as usize + 2)?) << 16;
+        }
+        for factory in &self.factories {
+            if let Some(instruction) = factory(instruction) {
+                return Ok(instruction);
+            }
+        }
+        Err(Error::InvalidInstruction(instruction))
+    }
+}
+
+pub fn build_rv32imac_decoder() -> Decoder {
+    let mut decoder = Decoder::new();
+    decoder.add_instruction_factory(rv32i::factory);
+    decoder
+}

src/instructions/mod.rs

@@ -0,0 +1,30 @@
+mod utils;
+
+pub mod rv32i;
+
+use super::machine::Machine;
+use super::Error;
+use std::fmt::{self, Display};
+
+#[derive(Debug)]
+pub enum Instruction {
+    RV32I(rv32i::Instruction),
+}
+
+impl Instruction {
+    pub fn execute(&self, machine: &mut Machine) -> Result<(), Error> {
+        match self {
+            Instruction::RV32I(instruction) => instruction.execute(machine),
+        }
+    }
+}
+
+impl Display for Instruction {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        // TODO: change to real disasm feature instead of simply delegating
+        // to std::fmt::Debug
+        write!(f, "{:?}", self)
+    }
+}
+
+pub type InstructionFactory = fn(instruction: u32) -> Option<Instruction>;

src/instructions/rv32i.rs

@@ -0,0 +1,32 @@
+use super::super::machine::Machine;
+use super::super::Error;
+use super::utils::{extract_opcode, extract_rd, extract_utype_immediate, update_register};
+use super::{Instruction as GenericInstruction, Instruction::RV32I};
+
+#[derive(Debug)]
+pub enum Instruction {
+    AUIPC(usize, u32),
+}
+
+impl Instruction {
+    pub fn execute(&self, machine: &mut Machine) -> Result<(), Error> {
+        match self {
+            Instruction::AUIPC(rd, imm) => {
+                let value = machine.pc + imm;
+                machine.pc += 4;
+                update_register(machine, *rd, value);
+            }
+        }
+        Ok(())
+    }
+}
+
+pub fn factory(instruction: u32) -> Option<GenericInstruction> {
+    match extract_opcode(instruction) {
+        0x17 => Some(RV32I(Instruction::AUIPC(
+            extract_rd(instruction),
+            extract_utype_immediate(instruction),
+        ))),
+        _ => None,
+    }
+}

src/instructions/utils.rs

@@ -0,0 +1,24 @@
+use super::super::machine::Machine;
+use RISCV_GENERAL_REGISTER_NUMBER;
+
+#[inline(always)]
+pub fn extract_opcode(instruction: u32) -> u32 {
+    instruction & 0x7F
+}
+
+#[inline(always)]
+pub fn extract_rd(instruction: u32) -> usize {
+    ((instruction >> 7) & 0x1F) as usize
+}
+
+#[inline(always)]
+pub fn extract_utype_immediate(instruction: u32) -> u32 {
+    instruction & 0xFFFF_F000
+}
+
+pub fn update_register(machine: &mut Machine, register_index: usize, value: u32) {
+    let register_index = register_index % RISCV_GENERAL_REGISTER_NUMBER;
+    if register_index > 0 {
+        machine.registers[register_index] = value;
+    }
+}

src/lib.rs

@@ -0,0 +1,31 @@
+extern crate byteorder;
+extern crate goblin;
+
+mod decoder;
+mod instructions;
+mod machine;
+mod memory;
+
+use machine::Machine;
+use std::io::Error as IOError;
+
+pub const RISCV_PAGESIZE: usize = 1 << 12;
+pub const RISCV_GENERAL_REGISTER_NUMBER: usize = 32;
+// 128 MB
+pub const RISCV_MAX_MEMORY: usize = 128 << 20;
+
+#[derive(Debug)]
+pub enum Error {
+    ParseError,
+    Alignment,
+    OutOfBound,
+    InvalidInstruction(u32),
+    IO(IOError),
+    Unimplemented,
+}
+
+pub fn run(program: &[u8], args: &[String]) -> Result<u8, Error> {
+    let mut machine = Machine::default();
+    machine.load(program)?;
+    machine.run(args)
+}

src/machine.rs

@@ -0,0 +1,61 @@
+use super::decoder::{build_rv32imac_decoder, Decoder};
+use super::memory::Memory;
+use super::{Error, RISCV_GENERAL_REGISTER_NUMBER, RISCV_MAX_MEMORY};
+use goblin::elf::program_header::PT_LOAD;
+use goblin::elf::Elf;
+
+pub struct Machine {
+    // TODO: while CKB doesn't need it, other environment could benefit from
+    // parameterized register size.
+    pub registers: [u32; RISCV_GENERAL_REGISTER_NUMBER],
+    pub pc: u32,
+    pub memory: Box<Memory>,
+
+    decoder: Decoder,
+    running: bool,
+    exit_code: u8,
+}
+
+impl Machine {
+    pub fn default() -> Machine {
+        // While a real machine might use whatever random data left in the memory(or
+        // random scrubbed data for security), we are initializing everything to 0 here
+        // for deterministic behavior.
+        Machine {
+            registers: [0; RISCV_GENERAL_REGISTER_NUMBER],
+            pc: 0,
+            // TODO: add real MMU object with proper permission checks, right now
+            // a flat buffer is enough for experimental use.
+            memory: Box::new(vec![0; RISCV_MAX_MEMORY]),
+            decoder: build_rv32imac_decoder(),
+            running: false,
+            exit_code: 0,
+        }
+    }
+
+    pub fn load(&mut self, program: &[u8]) -> Result<(), Error> {
+        let elf = Elf::parse(program).map_err(|_e| Error::ParseError)?;
+        for program_header in &elf.program_headers {
+            if program_header.p_type == PT_LOAD {
+                // TODO: page alignment
+                self.memory.mmap(
+                    program_header.p_vaddr as usize,
+                    program_header.p_filesz as usize,
+                    program,
+                    program_header.p_offset as usize,
+                )?;
+            }
+        }
+        self.pc = elf.header.e_entry as u32;
+        Ok(())
+    }
+
+    pub fn run(&mut self, _args: &[String]) -> Result<u8, Error> {
+        self.running = true;
+        while self.running {
+            let instruction = self.decoder.decode(self)?;
+            instruction.execute(self)?;
+        }
+        Ok(self.exit_code)
+    }
+}

src/memory.rs

@@ -0,0 +1,69 @@
+use super::Error;
+
+use byteorder::{LittleEndian, ReadBytesExt};
+use std::io::{Cursor, Seek, SeekFrom};
+
+pub trait Memory {
+    fn mmap(
+        &mut self,
+        addr: usize,
+        size: usize,
+        source: &[u8],
+        offset: usize,
+    ) -> Result<usize, Error>;
+
+    // TODO: maybe parameterize those?
+    fn load16(&self, addr: usize) -> Result<u16, Error>;
+    fn load32(&self, addr: usize) -> Result<u32, Error>;
+}
+
+// Here we build a flat memory based Memory object as a starting point for fast
+// iteration. Later we might want to re-evaluate this to see if we need a real
+// MMU system.
+// Current system is lacking the following features needed in a real production
+// system:
+//
+// * mmap should work on pages, not arbitrary memory segments
+// * disallow unaligned address on page boundary
+// * read/write/execute permission checking
+impl Memory for Vec<u8> {
+    fn mmap(
+        &mut self,
+        addr: usize,
+        size: usize,
+        source: &[u8],
+        offset: usize,
+    ) -> Result<usize, Error> {
+        if addr + size > self.len() || offset + size > source.len() {
+            return Err(Error::OutOfBound);
+        }
+        let (_, right) = self.split_at_mut(addr);
+        let (slice, _) = right.split_at_mut(size);
+        slice.copy_from_slice(&source[offset..offset + size]);
+        Ok(addr)
+    }
+
+    fn load16(&self, addr: usize) -> Result<u16, Error> {
+        if addr + 4 > self.len() {
+            return Err(Error::OutOfBound);
+        }
+        let mut reader = Cursor::new(&self);
+        reader
+            .seek(SeekFrom::Start(addr as u64))
+            .map_err(Error::IO)?;
+        // NOTE: Base RISC-V ISA is defined as a little-endian memory system.
+        reader.read_u16::<LittleEndian>().map_err(Error::IO)
+    }
+
+    fn load32(&self, addr: usize) -> Result<u32, Error> {
+        if addr + 4 > self.len() {
+            return Err(Error::OutOfBound);
+        }
+        let mut reader = Cursor::new(&self);
+        reader
+            .seek(SeekFrom::Start(addr as u64))
+            .map_err(Error::IO)?;
+        // NOTE: Base RISC-V ISA is defined as a little-endian memory system.
+        reader.read_u32::<LittleEndian>().map_err(Error::IO)
+    }
+}

tests/programs/minimal

@@ -0,0 +1,14 @@
+/*
+ * First, compile riscv-gnu-toolchain with `--with-arch=rv32imac --with-abi=ilp32`,
+ * then compile current file with riscv32-unknown-elf-gcc -o minimal minimal.c
+ */
+int main(int argc, char* argv[])
+{
+  if (argc == 1) {
+    return 1;
+  }
+  if (argv[1][0] == 'a') {
+    return 2;
+  }
+  return 0;
+}

tests/programs/minimal.c

@@ -0,0 +1,38 @@
+extern crate ckb_riscv;
+
+use ckb_riscv::run;
+use std::fs::File;
+use std::io::Read;
+
+#[test]
+pub fn test_minimal_with_no_args() {
+    let mut file = File::open("tests/programs/minimal").unwrap();
+    let mut buffer = Vec::new();
+    file.read_to_end(&mut buffer).unwrap();
+
+    let result = run(&buffer, &Vec::new());
+    assert!(result.is_ok());
+    assert_eq!(result.unwrap(), 1);
+}
+
+#[test]
+pub fn test_minimal_with_a() {
+    let mut file = File::open("tests/programs/minimal").unwrap();
+    let mut buffer = Vec::new();
+    file.read_to_end(&mut buffer).unwrap();
+
+    let result = run(&buffer, &vec!["a".to_string()]);
+    assert!(result.is_ok());
+    assert_eq!(result.unwrap(), 2);
+}
+
+#[test]
+pub fn test_minimal_with_b() {
+    let mut file = File::open("tests/programs/minimal").unwrap();
+    let mut buffer = Vec::new();
+    file.read_to_end(&mut buffer).unwrap();
+
+    let result = run(&buffer, &vec!["b".to_string()]);
+    assert!(result.is_ok());
+    assert_eq!(result.unwrap(), 0);
+}