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Snake.twr
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--------------------------------------------------------------------------------
Release 14.6 Trace (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
C:\Xilinx\14.6\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n
3 -fastpaths -xml Snake.twx Snake.ncd -o Snake.twr Snake.pcf -ucf
labkit_nexys3.ucf
Design file: Snake.ncd
Physical constraint file: Snake.pcf
Device,package,speed: xc6slx16,csg324,C,-3 (PRODUCTION 1.23 2013-06-08)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Setup/Hold to clock clk_100mhz
------------+------------+------------+------------+------------+------------------+--------+
|Max Setup to| Process |Max Hold to | Process | | Clock |
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
------------+------------+------------+------------+------------+------------------+--------+
btn_down | 4.077(R)| SLOW | -1.149(R)| FAST |clk_25mhz_BUFG | 0.000|
btn_left | 4.016(R)| SLOW | -1.073(R)| FAST |clk_25mhz_BUFG | 0.000|
btn_right | 4.714(R)| SLOW | -1.562(R)| FAST |clk_25mhz_BUFG | 0.000|
btn_up | 5.620(R)| SLOW | -1.997(R)| FAST |clk_25mhz_BUFG | 0.000|
switch<0> | 4.801(R)| SLOW | -1.608(R)| FAST |clk_25mhz_BUFG | 0.000|
switch<1> | 8.794(R)| SLOW | -2.276(R)| FAST |clk_25mhz_BUFG | 0.000|
switch<2> | 8.588(R)| SLOW | -2.474(R)| FAST |clk_25mhz_BUFG | 0.000|
switch<7> | 12.454(R)| SLOW | -1.755(R)| FAST |clk_25mhz_BUFG | 0.000|
------------+------------+------------+------------+------------+------------------+--------+
Clock clk_100mhz to Pad
------------+-----------------+------------+-----------------+------------+------------------+--------+
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
------------+-----------------+------------+-----------------+------------+------------------+--------+
hsync | 6.397(R)| SLOW | 4.196(R)| FAST |clk_25mhz_BUFG | 0.000|
vgablue<1> | 7.047(R)| SLOW | 4.582(R)| FAST |clk_25mhz_BUFG | 0.000|
vgablue<2> | 6.880(R)| SLOW | 4.453(R)| FAST |clk_25mhz_BUFG | 0.000|
vgagreen<0> | 7.090(R)| SLOW | 4.566(R)| FAST |clk_25mhz_BUFG | 0.000|
vgagreen<1> | 7.121(R)| SLOW | 4.605(R)| FAST |clk_25mhz_BUFG | 0.000|
vgagreen<2> | 7.288(R)| SLOW | 4.734(R)| FAST |clk_25mhz_BUFG | 0.000|
vgared<0> | 6.976(R)| SLOW | 4.482(R)| FAST |clk_25mhz_BUFG | 0.000|
vgared<1> | 6.816(R)| SLOW | 4.396(R)| FAST |clk_25mhz_BUFG | 0.000|
vgared<2> | 7.134(R)| SLOW | 4.564(R)| FAST |clk_25mhz_BUFG | 0.000|
vsync | 7.609(R)| SLOW | 4.839(R)| FAST |clk_25mhz_BUFG | 0.000|
------------+-----------------+------------+-----------------+------------+------------------+--------+
Clock to Setup on destination clock clk_100mhz
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_100mhz | 168.971| | | |
---------------+---------+---------+---------+---------+
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
switch<0> |led<0> | 7.332|
switch<1> |led<1> | 7.653|
switch<2> |led<2> | 7.342|
switch<3> |led<3> | 7.716|
switch<4> |led<4> | 6.943|
switch<5> |led<5> | 6.999|
switch<6> |led<6> | 6.932|
switch<7> |led<7> | 7.749|
---------------+---------------+---------+
Analysis completed Thu Nov 30 21:15:06 2017
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 200 MB