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update uart driver to use IO driver style #1

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merged 1 commit into from
Jun 26, 2015
+86 −164
Merged

update uart driver to use IO driver style #1

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29 changes: 15 additions & 14 deletions source/common/hal/freescale/kl26z/IO_Config.h
View file
Original file line number Diff line number Diff line change
@@ -24,57 +24,57 @@
// SWCLK Pin PTC5(C5)
#define PIN_SWCLK_PORT PORTC
#define PIN_SWCLK_GPIO PTC
#define PIN_SWCLK_BIT 5
#define PIN_SWCLK_BIT (5)
#define PIN_SWCLK (1<<PIN_SWCLK_BIT)

// SWDIO Pin PTC6(C6)
#define PIN_SWDIO_PORT PORTC
#define PIN_SWDIO_GPIO PTC
#define PIN_SWDIO_BIT 6
#define PIN_SWDIO_BIT (6)
#define PIN_SWDIO (1<<PIN_SWDIO_BIT)

// nRESET Pin PTC8(C8)
#define PIN_nRESET_PORT PORTC
#define PIN_nRESET_GPIO PTC
#define PIN_nRESET_BIT 8
#define PIN_nRESET_BIT (8)
#define PIN_nRESET (1<<PIN_nRESET_BIT)

// PWR_REG_EN PTD2 - Not connected
#define PIN_POWER_EN_PORT PORTD
#define PIN_POWER_EN_GPIO PTD
#define PIN_POWER_EN_BIT 2
#define PIN_POWER_EN_BIT (2)
#define PIN_POWER_EN (1<<PIN_POWER_EN_BIT)

// VTRG_FAULT_B PTD3 - Not connected
#define PIN_VTRG_FAULT_B_PORT PORTD
#define PIN_VTRG_FAULT_B_GPIO PTD
#define PIN_VTRG_FAULT_B_BIT 7
#define PIN_VTRG_FAULT_B_BIT (7)
#define PIN_VTRG_FAULT_B_EN (1<<PIN_VTRG_FAULT_B_BIT)

// Debug Unit LEDs

// HID_LED PTD4
#define PIN_HID_LED_PORT PORTD
#define PIN_HID_LED_GPIO PTD
#define PIN_HID_LED_BIT 4
#define PIN_HID_LED_BIT (4)
#define PIN_HID_LED (1<<PIN_HID_LED_BIT)

// MSC_LED PTD5
#define PIN_MSC_LED_PORT PORTD
#define PIN_MSC_LED_GPIO PTD
#define PIN_MSC_LED_BIT 4
#define PIN_MSC_LED_BIT (4)
#define PIN_MSC_LED (1<<PIN_MSC_LED_BIT)

// CDC_LED PTD6
#define PIN_CDC_LED_PORT PORTD
#define PIN_CDC_LED_GPIO PTD
#define PIN_CDC_LED_BIT 4
#define PIN_CDC_LED_BIT (4)
#define PIN_CDC_LED (1<<PIN_CDC_LED_BIT)

// SW RESET BUTTON PTB1
#define PIN_SW_RESET_PORT PORTB
#define PIN_SW_RESET_GPIO PTB
#define PIN_SW_RESET_BIT 1
#define PIN_SW_RESET_BIT (1)
#define PIN_SW_RESET (1<<PIN_SW_RESET_BIT)

// Connected LED Not available
@@ -87,16 +87,17 @@

// UART
#define UART_PORT PORTC
#define UART_NUM (1)
// RX PTC3
#define PIN_UART_RX_GPIO PTC
#define PIN_UART_RX_BIT 3
#define PIN_UART_RX_BIT (3)
#define PIN_UART_RX (1<<PIN_UART_RX_BIT)
#define PIN_UART_RX_MUX_ALT 3
#define PIN_UART_RX_MUX_ALT (3)
// TX PTC4
#define PIN_UART_TX_GPIO PTC
#define PIN_UART_TX_BIT 4
#define PIN_UART_TX (1<<PIN_UART_RX_BIT)
#define PIN_UART_TX_MUX_ALT 3
#define PIN_UART_TX_BIT (4)
#define PIN_UART_TX (1<<PIN_UART_TX_BIT)
#define PIN_UART_TX_MUX_ALT (3)

#define UART UART1
#define UART_RX_TX_IRQn UART1_IRQn
221 changes: 71 additions & 150 deletions source/common/hal/freescale/kl26z/uart.c
View file
Original file line number Diff line number Diff line change
@@ -13,46 +13,16 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined(INTERFACE_KL26Z)
#include "MKL26Z4.h"
#else
#error "Unknown target type"
#endif

#include "uart.h"
#include "IO_Config.h"
#include "string.h"

// Serial PTC3, PTC4
#define UART_NO 1
#define TARGET_UART_PORT PORTC
#define TARGET_UART_RX_PIN 3
#define TARGET_UART_TX_PIN 4
#define TARGET_UART_ALT 3

#if UART_NO==0
#define TARGET_UART UART0
#define TARGET_UART_RX_TX_IRQn UART0_IRQn
#define TARGET_UART_RX_TX_IRQHandler UART0_IRQHandler
#elif UART_NO==1
#define TARGET_UART UART1
#define TARGET_UART_RX_TX_IRQn UART1_IRQn
#define TARGET_UART_RX_TX_IRQHandler UART1_IRQHandler
#elif UART_NO==2
#define TARGET_UART UART2
#define TARGET_UART_RX_TX_IRQn UART2_IRQn
#define TARGET_UART_RX_TX_IRQHandler UART2_IRQHandler
#else
#error target error
#endif

extern uint32_t SystemCoreClock;

static void clear_buffers(void);

// Size must be 2^n for using quick wrap around
#define BUFFER_SIZE (64)
#define UART_BUFFER_SIZE (64)

struct {
uint8_t data[BUFFER_SIZE];
uint8_t data[UART_BUFFER_SIZE];
volatile uint32_t idx_in;
volatile uint32_t idx_out;
volatile uint32_t cnt_in;
@@ -75,100 +45,81 @@ void clear_buffers(void)
write_buffer.cnt_out = 0;
}

int32_t uart_initialize (void) {

NVIC_DisableIRQ(TARGET_UART_RX_TX_IRQn);

int32_t uart_initialize(void)
{
NVIC_DisableIRQ(UART_RX_TX_IRQn);
clear_buffers();

// enable clk port
if (TARGET_UART_PORT == PORTA) {
if (UART_PORT == PORTA) {
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
}
if (TARGET_UART_PORT == PORTC) {
if (UART_PORT == PORTC) {
SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
}
if (TARGET_UART_PORT == PORTD) {
if (UART_PORT == PORTD) {
SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK;
}
if (TARGET_UART_PORT == PORTE) {
if (UART_PORT == PORTE) {
SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;
}
// enable clk uart
if (UART_NO==1) {
if (1 == UART_NUM) {
SIM->SCGC4 |= SIM_SCGC4_UART1_MASK;
}
if (UART_NO==2) {
if (2 == UART_NUM) {
SIM->SCGC4 |= SIM_SCGC4_UART2_MASK;
}
// alternate setting
TARGET_UART_PORT->PCR[TARGET_UART_RX_PIN] = (TARGET_UART_ALT << 8);
TARGET_UART_PORT->PCR[TARGET_UART_TX_PIN] = (TARGET_UART_ALT << 8);

UART_PORT->PCR[PIN_UART_RX_BIT] = PORT_PCR_MUX(PIN_UART_RX_MUX_ALT);
UART_PORT->PCR[PIN_UART_TX_BIT] = PORT_PCR_MUX(PIN_UART_TX_MUX_ALT);
// transmitter and receiver enabled
TARGET_UART->C2 |= UART_C2_RE_MASK | UART_C2_TE_MASK;

UART->C2 |= UART_C2_RE_MASK | UART_C2_TE_MASK;
// Enable receive interrupt
TARGET_UART->C2 |= UART_C2_RIE_MASK;

NVIC_ClearPendingIRQ(TARGET_UART_RX_TX_IRQn);

NVIC_EnableIRQ(TARGET_UART_RX_TX_IRQn);

UART->C2 |= UART_C2_RIE_MASK;
NVIC_ClearPendingIRQ(UART_RX_TX_IRQn);
NVIC_EnableIRQ(UART_RX_TX_IRQn);
return 1;
}

int32_t uart_uninitialize (void) {

int32_t uart_uninitialize(void)
{
// transmitter and receiver disabled
TARGET_UART->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);

UART->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
// disable interrupt
TARGET_UART->C2 &= ~(UART_C2_RIE_MASK | UART_C2_TIE_MASK);

UART->C2 &= ~(UART_C2_RIE_MASK | UART_C2_TIE_MASK);
clear_buffers();

return 1;
}

int32_t uart_reset (void) {

int32_t uart_reset(void)
{
// disable interrupt
NVIC_DisableIRQ (TARGET_UART_RX_TX_IRQn);

NVIC_DisableIRQ(UART_RX_TX_IRQn);
clear_buffers();

// disable TIE interrupt
TARGET_UART->C2 &= ~(UART_C2_TIE_MASK);

UART->C2 &= ~(UART_C2_TIE_MASK);
tx_in_progress = 0;

// enable interrupt
NVIC_EnableIRQ (TARGET_UART_RX_TX_IRQn);

NVIC_EnableIRQ(UART_RX_TX_IRQn);
return 1;
}

int32_t uart_set_configuration (UART_Configuration *config) {

int32_t uart_set_configuration(UART_Configuration *config)
{
uint8_t data_bits = 8;
uint8_t parity_enable = 0;
uint8_t parity_type = 0;
uint32_t dll;

// disable interrupt
NVIC_DisableIRQ (TARGET_UART_RX_TX_IRQn);
NVIC_DisableIRQ(UART_RX_TX_IRQn);
// Disable receiver and transmitter while updating
TARGET_UART->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);

UART->C2 &= ~(UART_C2_RE_MASK | UART_C2_TE_MASK);
clear_buffers();

// set data bits, stop bits, parity
if ((config->DataBits < 8) || (config->DataBits > 9)) {
data_bits = 8;
}
data_bits -= 8;

if (config->Parity == 1) {
parity_enable = 1;
parity_type = 1;
@@ -178,151 +129,121 @@ int32_t uart_set_configuration (UART_Configuration *config) {
parity_type = 0;
data_bits++;
}

// does not support 10 bit data comm
if (data_bits == 2) {
data_bits = 0;
parity_enable = 0;
parity_type = 0;
}

// data bits, parity and parity mode
TARGET_UART->C1 = data_bits << UART_C1_M_SHIFT
| parity_enable << UART_C1_PE_SHIFT
| parity_type << UART_C1_PT_SHIFT;
UART->C1 = data_bits << UART_C1_M_SHIFT |
parity_enable << UART_C1_PE_SHIFT |
parity_type << UART_C1_PT_SHIFT;

dll = SystemCoreClock / (16 * config->Baudrate);

if (UART_NO == 1 || UART_NO == 2) {
dll /= 2;
if (1 == UART_NUM || 2 == UART_NUM) {
dll /= 2; //TODO <<= 1
}
// set baudrate
TARGET_UART->BDH = (TARGET_UART->BDH & ~(UART_BDH_SBR_MASK)) | ((dll >> 8) & UART_BDH_SBR_MASK);
TARGET_UART->BDL = (TARGET_UART->BDL & ~(UART_BDL_SBR_MASK)) | (dll & UART_BDL_SBR_MASK);

UART->BDH = (UART->BDH & ~(UART_BDH_SBR_MASK)) | ((dll >> 8) & UART_BDH_SBR_MASK);
UART->BDL = (UART->BDL & ~(UART_BDL_SBR_MASK)) | (dll & UART_BDL_SBR_MASK);
// Enable transmitter and receiver
TARGET_UART->C2 |= UART_C2_RE_MASK | UART_C2_TE_MASK;

UART->C2 |= UART_C2_RE_MASK | UART_C2_TE_MASK;
// Enable UART interrupt
NVIC_ClearPendingIRQ (TARGET_UART_RX_TX_IRQn);
NVIC_EnableIRQ (TARGET_UART_RX_TX_IRQn);

NVIC_ClearPendingIRQ(UART_RX_TX_IRQn);
NVIC_EnableIRQ(UART_RX_TX_IRQn);
return 1;
}

int32_t uart_get_configuration (UART_Configuration *config) {

int32_t uart_get_configuration(UART_Configuration *config)
{
return 1;
}

int32_t uart_write_free(void) {

return BUFFER_SIZE - (write_buffer.cnt_in - write_buffer.cnt_out);
int32_t uart_write_free(void)
{
return UART_BUFFER_SIZE - (write_buffer.cnt_in - write_buffer.cnt_out);
}

int32_t uart_write_data (uint8_t *data, uint16_t size) {
int32_t uart_write_data (uint8_t *data, uint16_t size)
{
uint32_t cnt;
int16_t len_in_buf;

if (size == 0) {
return 0;
}

cnt = 0;

while (size--) {
len_in_buf = write_buffer.cnt_in - write_buffer.cnt_out;
if (len_in_buf < BUFFER_SIZE) {
if (len_in_buf < UART_BUFFER_SIZE) {
write_buffer.data[write_buffer.idx_in++] = *data++;
write_buffer.idx_in &= (BUFFER_SIZE - 1);
write_buffer.idx_in &= (UART_BUFFER_SIZE - 1);
write_buffer.cnt_in++;
cnt++;
}
}

if (!tx_in_progress)
{
if (!tx_in_progress) {
// Wait for D register to be free
while(!(TARGET_UART->S1 & UART_S1_TDRE_MASK)) { }

while(!(UART->S1 & UART_S1_TDRE_MASK));
tx_in_progress = 1;

// Write the first byte into D
UART1->D = write_buffer.data[write_buffer.idx_out++];
write_buffer.idx_out &= (BUFFER_SIZE - 1);
write_buffer.idx_out &= (UART_BUFFER_SIZE - 1);
write_buffer.cnt_out++;

// enable TX interrupt
TARGET_UART->C2 |= UART_C2_TIE_MASK;
UART->C2 |= UART_C2_TIE_MASK;
}

return cnt;
}

int32_t uart_read_data (uint8_t *data, uint16_t size) {
int32_t uart_read_data(uint8_t *data, uint16_t size)
{
uint32_t cnt;

if (size == 0) {
return 0;
}

cnt = 0;

while (size--) {
if (read_buffer.cnt_in != read_buffer.cnt_out) {
*data++ = read_buffer.data[read_buffer.idx_out++];
read_buffer.idx_out &= (BUFFER_SIZE - 1);
read_buffer.idx_out &= (UART_BUFFER_SIZE - 1);
read_buffer.cnt_out++;
cnt++;
}
else
{
} else {
break;
}
}

return cnt;
}

void TARGET_UART_RX_TX_IRQHandler (void) {
void UART_RX_TX_IRQHandler(void)
{
uint32_t s1;
volatile uint8_t errorData;

// read interrupt status
s1 = TARGET_UART->S1;

s1 = UART->S1;
// handle character to transmit
if (write_buffer.cnt_in != write_buffer.cnt_out) {
// if TDRE is empty
if (s1 & UART_S1_TDRE_MASK) {
TARGET_UART->D = write_buffer.data[write_buffer.idx_out++];
write_buffer.idx_out &= (BUFFER_SIZE - 1);
UART->D = write_buffer.data[write_buffer.idx_out++];
write_buffer.idx_out &= (UART_BUFFER_SIZE - 1);
write_buffer.cnt_out++;
tx_in_progress = 1;
}
}
else {
} else {
// disable TIE interrupt
TARGET_UART->C2 &= ~(UART_C2_TIE_MASK);
UART->C2 &= ~(UART_C2_TIE_MASK);
tx_in_progress = 0;
}

// handle received character
if (s1 & UART_S1_RDRF_MASK) {
if ((s1 & UART_S1_NF_MASK) || (s1 & UART_S1_FE_MASK))
{
errorData = TARGET_UART->D;
}
else
{
read_buffer.data[read_buffer.idx_in++] = TARGET_UART->D;
read_buffer.idx_in &= (BUFFER_SIZE - 1);
if ((s1 & UART_S1_NF_MASK) || (s1 & UART_S1_FE_MASK)) {
errorData = UART->D;
} else {
read_buffer.data[read_buffer.idx_in++] = UART->D;
read_buffer.idx_in &= (UART_BUFFER_SIZE - 1);
read_buffer.cnt_in++;
}
}
}

/*------------------------------------------------------------------------------
* End of file
*----------------------------------------------------------------------------*/