EECS 151/251A FPGA Project Skeleton for Spring 2025

Check out the Project Overview to see the specs.

Checkpoint 1: 3-Stage RISC-V (rv32ui) Processor Block Design Diagram

Checkpoint 2: Basic 3-Stage RISC-V (rv32ui) Processor Implementation

Checkpoint 3: Fully Functional 3-Stage RISC-V (rv32ui) Processor on FPGA

Checkpoint 4: Processor Optimization

Resources:

• RISC-V ISA Manual (Sections 2.2 - 2.6)