This is an implementation of a 5 stage fully pipelined and optimized CPU in verilog following the MIPS/RISC V design along with the design of dedicated I-Cache and D-Cache with a Unified L2-Cache mechanism. The details of the implementation can be found in the Project Description PDF and this project was completed for ECE 552 for Fall 2024 at the University of Wisconsin - Madison.
NOTE: The final implementation of the stacked Cache Controller design integration with CPU was INCOMPLETE. Read Project Report for details.