verilog-uart

A UART transceiver written in verilog. The individual transmitter and receiver modules are also included.

Modules

Module documentation is included in each module file.

• uart.v - UART serial transceiver
• uart_tx.v - UART serial transmitter
• uart_rx.v - UART serial receiver

Repository Structure

• /max_v_dev_kit - Run the UART on the Max V development kit
• /test - Test bench files
• /verilog - Verilog source code