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CAD & Reliability Group

Works produced by the CAD & Reliability group of the Department of Control and Computer Engineering (DAUIN) of Politecnico di Torino

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The Electronic CAD & Reliability Group is a research group inside the Department of Control and Computer Engineering (DAUIN) of Politecnico di Torino. Its mission is to support, through techniques, tools, and services, the designer of electronic circuits and systems. The research conducted by the group spans the whole spectrum of classical computer-aided design topics, with particular emphasis on testing, fault tolerance, and validation of digital circuits and systems described at various levels of abstraction.

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  1. I99T Public

    ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino

    VHDL 54 17

  2. byron Public

    An evolutionary source-code fuzzer

    Jupyter Notebook 11 1

  3. testcrush Public

    A Software Test Library compaction tool based on VC-Z01X.

    Python 2 2

Repositories

Showing 10 of 17 repositories
  • testcrush Public

    A Software Test Library compaction tool based on VC-Z01X.

    Python 2 MIT 2 0 1 Updated Mar 19, 2025
  • dnn-benchmarks Public

    This repository is a comprehensive collection of benchmarks for Deep Neural Networks (DNNs), designed to evaluate and compare the performance of various models across different hardware configurations, frameworks, and datasets.

    Python 1 Apache-2.0 0 0 0 Updated Mar 8, 2025
  • SFIadvancedmodels Public

    Fault injection tool for reliability assessment of deep learning algorithm such as Neural Networks

    Python 0 1 0 0 Updated Mar 5, 2025
  • byron Public

    An evolutionary source-code fuzzer

    Jupyter Notebook 11 Apache-2.0 1 0 6 Updated Jan 7, 2025
  • ase_riscv_gem5_sim Public

    RISCV Gem5 simulator flow for Architetture dei Sistemi di Elaborazione

    Python 12 GPL-2.0 2 1 1 Updated Oct 22, 2024
  • pulpino_ri5cy_stls Public

    Stuck-At Software Test Libraries for the pulpino-ri5cy SoC

    Assembly 4 Apache-2.0 0 0 0 Updated May 29, 2024
  • r4ves Public

    RiscV Environment for Simulation (R4VES) is a generic and modular framework that eases the grunt work required in order to perform pre/post-synthesis logic and fault simulation on RISC-V cores based on Model/QuestaSim and Z01X.

    Verilog 1 Apache-2.0 1 0 0 Updated May 28, 2024
  • Python 0 1 0 0 Updated Apr 26, 2024
  • x-heep-femu-tflite-sdk Public Forked from esl-epfl/x-heep-femu-sdk

    X-HEEP-based FPGA EMUlation Platform (FEMU) Software Development Kit (SDK) with Tensorflow Lite for Microcontrollers support.

    C 0 9 0 0 Updated Apr 26, 2024
  • C++ 0 Apache-2.0 0 0 0 Updated Mar 2, 2024