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🐛 Fixed design_sidb_gates function for skeletons with east-facing I/O pins. #594

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merged 12 commits into from
Nov 26, 2024

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Drewniok
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@Drewniok Drewniok commented Nov 25, 2024

Description

This PR fixes the following bug in the design_sidb_gates function: When using a gate skeleton with wires facing east, the gate design would not work.

The error occurred during the second pruning step when using QuickCell for designing SiDB gates. During this step, the feasibility of the physical validity is checked by toggling through different input patterns and adjusting the charge distribution of the I/O pins accordingly. However, the logic failed for I/O pins facing east because this specific case was not accounted for in the if statement. This is now fixed.

Checklist:

  • The pull request only contains commits that are related to it.
  • I have added appropriate tests and documentation.
  • I have added a changelog entry.
  • I have created/adjusted the Python bindings for any new or updated functionality.
  • I have made sure that all CI jobs on GitHub pass.
  • The pull request introduces no new warnings and follows the project's style guidelines.

Drewniok and others added 2 commits November 25, 2024 14:57
@Drewniok Drewniok added the bug Something isn't working label Nov 25, 2024
@Drewniok Drewniok self-assigned this Nov 25, 2024
@Drewniok Drewniok requested a review from marcelwa November 25, 2024 14:11
@Drewniok Drewniok changed the title 🐛 Fix gate skeleton bug for east-facing wires 🐛 Fixed gate design for skeletons with east-facing I/O pins. Nov 25, 2024
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codecov bot commented Nov 25, 2024

Codecov Report

All modified and coverable lines are covered by tests ✅

Project coverage is 98.12%. Comparing base (1cd3597) to head (d5e7de6).
Report is 118 commits behind head on main.

Additional details and impacted files

Impacted file tree graph

@@           Coverage Diff           @@
##             main     #594   +/-   ##
=======================================
  Coverage   98.11%   98.12%           
=======================================
  Files         232      232           
  Lines       35370    35410   +40     
  Branches     1707     1691   -16     
=======================================
+ Hits        34704    34746   +42     
+ Misses        666      664    -2     
Files with missing lines Coverage Δ
...n/algorithms/physical_design/design_sidb_gates.hpp 91.59% <100.00%> (+1.10%) ⬆️
...tion/algorithms/simulation/sidb/is_operational.hpp 97.94% <100.00%> (-0.14%) ⬇️
...t/algorithms/physical_design/design_sidb_gates.cpp 100.00% <100.00%> (ø)
test/utils/blueprints/layout_blueprints.hpp 100.00% <100.00%> (ø)

... and 1 file with indirect coverage changes


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clang-tidy review says "All clean, LGTM! 👍"

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clang-tidy review says "All clean, LGTM! 👍"

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clang-tidy review says "All clean, LGTM! 👍"

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clang-tidy review says "All clean, LGTM! 👍"

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clang-tidy review says "All clean, LGTM! 👍"

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clang-tidy review says "All clean, LGTM! 👍"

@Drewniok Drewniok changed the title 🐛 Fixed gate design for skeletons with east-facing I/O pins. 🐛 Fixed design_sidb_gates function for skeletons with east-facing I/O pins. Nov 26, 2024
@Drewniok Drewniok requested a review from marcelwa November 26, 2024 11:22
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clang-tidy review says "All clean, LGTM! 👍"

@Drewniok Drewniok merged commit 15c05fe into cda-tum:main Nov 26, 2024
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3 participants