[CodeGen][NewPM] Port SlotIndexes to new pass manager
#97941
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@llvm/pr-subscribers-backend-hexagon @llvm/pr-subscribers-backend-powerpc Author: None (paperchalice) Changes
Patch is 43.70 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/97941.diff 42 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/SlotIndexes.h b/llvm/include/llvm/CodeGen/SlotIndexes.h
index 21a9df22c2e1c..e29fd47cfec30 100644
--- a/llvm/include/llvm/CodeGen/SlotIndexes.h
+++ b/llvm/include/llvm/CodeGen/SlotIndexes.h
@@ -28,6 +28,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBundle.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/Support/Allocator.h"
#include <algorithm>
#include <cassert>
@@ -293,7 +294,9 @@ class raw_ostream;
/// SlotIndexes pass.
///
/// This pass assigns indexes to each instruction.
- class SlotIndexes : public MachineFunctionPass {
+ class SlotIndexes {
+ friend class SlotIndexesWrapperPass;
+
private:
// IndexListEntry allocator.
BumpPtrAllocator ileAllocator;
@@ -327,16 +330,17 @@ class raw_ostream;
void renumberIndexes(IndexList::iterator curItr);
public:
- static char ID;
+ SlotIndexes() = default;
- SlotIndexes();
+ SlotIndexes(SlotIndexes &&) = default;
- ~SlotIndexes() override;
+ SlotIndexes(MachineFunction &MF) { analyze(MF); }
- void getAnalysisUsage(AnalysisUsage &au) const override;
- void releaseMemory() override;
+ ~SlotIndexes();
- bool runOnMachineFunction(MachineFunction &fn) override;
+ bool analyze(MachineFunction &MF);
+
+ void print(raw_ostream &OS) const;
/// Dump the indexes.
void dump() const;
@@ -629,6 +633,43 @@ class raw_ostream;
struct IntervalMapInfo<SlotIndex> : IntervalMapHalfOpenInfo<SlotIndex> {
};
+ class SlotIndexesAnalysis : public AnalysisInfoMixin<SlotIndexesAnalysis> {
+ friend AnalysisInfoMixin<SlotIndexesAnalysis>;
+ static AnalysisKey Key;
+
+ public:
+ using Result = SlotIndexes;
+ Result run(MachineFunction &MF, MachineFunctionAnalysisManager &);
+ };
+
+ class SlotIndexesPrinterPass : public PassInfoMixin<SlotIndexesPrinterPass> {
+ raw_ostream &OS;
+
+ public:
+ explicit SlotIndexesPrinterPass(raw_ostream &OS) : OS(OS) {}
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+ static bool isRequired() { return true; }
+ };
+
+ class SlotIndexesWrapperPass : public MachineFunctionPass {
+ SlotIndexes SI;
+
+ public:
+ static char ID;
+
+ SlotIndexesWrapperPass();
+
+ void getAnalysisUsage(AnalysisUsage &au) const override;
+ void releaseMemory() override;
+
+ bool runOnMachineFunction(MachineFunction &fn) override {
+ return SI.analyze(fn);
+ }
+
+ SlotIndexes &getSI() { return SI; }
+ };
+
} // end namespace llvm
#endif // LLVM_CODEGEN_SLOTINDEXES_H
diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h
index 421c09ada7a19..b46a80f2eaa78 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -279,7 +279,7 @@ void initializeShrinkWrapPass(PassRegistry&);
void initializeSingleLoopExtractorPass(PassRegistry&);
void initializeSinkingLegacyPassPass(PassRegistry&);
void initializeSjLjEHPreparePass(PassRegistry&);
-void initializeSlotIndexesPass(PassRegistry&);
+void initializeSlotIndexesWrapperPassPass(PassRegistry &);
void initializeSpeculativeExecutionLegacyPassPass(PassRegistry&);
void initializeSpillPlacementPass(PassRegistry&);
void initializeStackColoringPass(PassRegistry&);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def
index b1542ab139286..706fa3fee74f8 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -95,6 +95,7 @@ MACHINE_FUNCTION_ANALYSIS("machine-dom-tree", MachineDominatorTreeAnalysis())
MACHINE_FUNCTION_ANALYSIS("machine-post-dom-tree",
MachinePostDominatorTreeAnalysis())
MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC))
+MACHINE_FUNCTION_ANALYSIS("slot-indexes", SlotIndexesAnalysis())
// LiveVariables currently requires pure SSA form.
// FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
// LiveVariables can be removed completely, and LiveIntervals can be directly
@@ -103,7 +104,6 @@ MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PI
// MACHINE_FUNCTION_ANALYSIS("live-vars", LiveVariablesAnalysis())
// MACHINE_FUNCTION_ANALYSIS("live-stacks", LiveStacksPass())
-// MACHINE_FUNCTION_ANALYSIS("slot-indexes", SlotIndexesAnalysis())
// MACHINE_FUNCTION_ANALYSIS("edge-bundles", EdgeBundlesAnalysis())
// MACHINE_FUNCTION_ANALYSIS("lazy-machine-bfi",
// LazyMachineBlockFrequencyInfoAnalysis())
@@ -138,6 +138,7 @@ MACHINE_FUNCTION_PASS("print<machine-dom-tree>",
MachineDominatorTreePrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("print<machine-post-dom-tree>",
MachinePostDominatorTreePrinterPass(dbgs()))
+MACHINE_FUNCTION_PASS("print<slot-indexes>", SlotIndexesPrinterPass(dbgs()))
MACHINE_FUNCTION_PASS("require-all-machine-function-properties",
RequireAllMachineFunctionPropertiesPass())
MACHINE_FUNCTION_PASS("trigger-verifier-error", TriggerVerifierErrorPass())
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 7dcb0ea5d903c..3d7d52515a59c 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -123,7 +123,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializeShadowStackGCLoweringPass(Registry);
initializeShrinkWrapPass(Registry);
initializeSjLjEHPreparePass(Registry);
- initializeSlotIndexesPass(Registry);
+ initializeSlotIndexesWrapperPassPass(Registry);
initializeStackColoringPass(Registry);
initializeStackFrameLayoutAnalysisPassPass(Registry);
initializeStackMapLivenessPass(Registry);
diff --git a/llvm/lib/CodeGen/LiveIntervals.cpp b/llvm/lib/CodeGen/LiveIntervals.cpp
index f9162b444e03d..99621d23b61c0 100644
--- a/llvm/lib/CodeGen/LiveIntervals.cpp
+++ b/llvm/lib/CodeGen/LiveIntervals.cpp
@@ -62,7 +62,7 @@ char &llvm::LiveIntervalsID = LiveIntervals::ID;
INITIALIZE_PASS_BEGIN(LiveIntervals, "liveintervals", "Live Interval Analysis",
false, false)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
-INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
+INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_END(LiveIntervals, "liveintervals",
"Live Interval Analysis", false, false)
@@ -89,8 +89,8 @@ void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreservedID(MachineLoopInfoID);
AU.addRequiredTransitiveID(MachineDominatorsID);
AU.addPreservedID(MachineDominatorsID);
- AU.addPreserved<SlotIndexes>();
- AU.addRequiredTransitive<SlotIndexes>();
+ AU.addPreserved<SlotIndexesWrapperPass>();
+ AU.addRequiredTransitive<SlotIndexesWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -122,7 +122,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
MRI = &MF->getRegInfo();
TRI = MF->getSubtarget().getRegisterInfo();
TII = MF->getSubtarget().getInstrInfo();
- Indexes = &getAnalysis<SlotIndexes>();
+ Indexes = &getAnalysis<SlotIndexesWrapperPass>().getSI();
DomTree = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
if (!LICalc)
diff --git a/llvm/lib/CodeGen/LiveStacks.cpp b/llvm/lib/CodeGen/LiveStacks.cpp
index 8fc5a929d77b2..ae36b2819a358 100644
--- a/llvm/lib/CodeGen/LiveStacks.cpp
+++ b/llvm/lib/CodeGen/LiveStacks.cpp
@@ -23,7 +23,7 @@ using namespace llvm;
char LiveStacks::ID = 0;
INITIALIZE_PASS_BEGIN(LiveStacks, DEBUG_TYPE,
"Live Stack Slot Analysis", false, false)
-INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
+INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_END(LiveStacks, DEBUG_TYPE,
"Live Stack Slot Analysis", false, false)
@@ -31,8 +31,8 @@ char &llvm::LiveStacksID = LiveStacks::ID;
void LiveStacks::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesAll();
- AU.addPreserved<SlotIndexes>();
- AU.addRequiredTransitive<SlotIndexes>();
+ AU.addPreserved<SlotIndexesWrapperPass>();
+ AU.addRequiredTransitive<SlotIndexesWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
diff --git a/llvm/lib/CodeGen/MLRegAllocPriorityAdvisor.cpp b/llvm/lib/CodeGen/MLRegAllocPriorityAdvisor.cpp
index 8c1bb41f1430c..9638df81770c1 100644
--- a/llvm/lib/CodeGen/MLRegAllocPriorityAdvisor.cpp
+++ b/llvm/lib/CodeGen/MLRegAllocPriorityAdvisor.cpp
@@ -134,7 +134,7 @@ class ReleaseModePriorityAdvisorAnalysis final
private:
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesAll();
- AU.addRequired<SlotIndexes>();
+ AU.addRequired<SlotIndexesWrapperPass>();
RegAllocPriorityAdvisorAnalysis::getAnalysisUsage(AU);
}
@@ -151,7 +151,7 @@ class ReleaseModePriorityAdvisorAnalysis final
InteractiveChannelBaseName + ".in");
}
return std::make_unique<MLPriorityAdvisor>(
- MF, RA, &getAnalysis<SlotIndexes>(), Runner.get());
+ MF, RA, &getAnalysis<SlotIndexesWrapperPass>().getSI(), Runner.get());
}
std::unique_ptr<MLModelRunner> Runner;
};
@@ -215,7 +215,7 @@ class DevelopmentModePriorityAdvisorAnalysis final
private:
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesAll();
- AU.addRequired<SlotIndexes>();
+ AU.addRequired<SlotIndexesWrapperPass>();
RegAllocPriorityAdvisorAnalysis::getAnalysisUsage(AU);
}
@@ -266,7 +266,8 @@ class DevelopmentModePriorityAdvisorAnalysis final
}
return std::make_unique<DevelopmentModePriorityAdvisor>(
- MF, RA, &getAnalysis<SlotIndexes>(), Runner.get(), Log.get());
+ MF, RA, &getAnalysis<SlotIndexesWrapperPass>().getSI(), Runner.get(),
+ Log.get());
}
std::unique_ptr<MLModelRunner> Runner;
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 533ab7cccaeb7..35a449e761a0a 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -1162,7 +1162,8 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
<< printMBBReference(*Succ) << '\n');
LiveIntervals *LIS = P.getAnalysisIfAvailable<LiveIntervals>();
- SlotIndexes *Indexes = P.getAnalysisIfAvailable<SlotIndexes>();
+ auto *SIWrapper = P.getAnalysisIfAvailable<SlotIndexesWrapperPass>();
+ SlotIndexes *Indexes = SIWrapper ? &SIWrapper->getSI() : nullptr;
if (LIS)
LIS->insertMBBInMaps(NMBB);
else if (Indexes)
diff --git a/llvm/lib/CodeGen/MachineFunctionPrinterPass.cpp b/llvm/lib/CodeGen/MachineFunctionPrinterPass.cpp
index c31c065b19767..0f88a7b741600 100644
--- a/llvm/lib/CodeGen/MachineFunctionPrinterPass.cpp
+++ b/llvm/lib/CodeGen/MachineFunctionPrinterPass.cpp
@@ -39,7 +39,7 @@ struct MachineFunctionPrinterPass : public MachineFunctionPass {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesAll();
- AU.addUsedIfAvailable<SlotIndexes>();
+ AU.addUsedIfAvailable<SlotIndexesWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -47,7 +47,8 @@ struct MachineFunctionPrinterPass : public MachineFunctionPass {
if (!isFunctionInPrintList(MF.getName()))
return false;
OS << "# " << Banner << ":\n";
- MF.print(OS, getAnalysisIfAvailable<SlotIndexes>());
+ auto *SIWrapper = getAnalysisIfAvailable<SlotIndexesWrapperPass>();
+ MF.print(OS, SIWrapper ? &SIWrapper->getSI() : nullptr);
return false;
}
};
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 4a6d5edcfc885..943c948b994d9 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -268,7 +268,7 @@ INITIALIZE_PASS_BEGIN(MachineScheduler, DEBUG_TYPE,
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
-INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
+INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
INITIALIZE_PASS_END(MachineScheduler, DEBUG_TYPE,
"Machine Instruction Scheduler", false, false)
@@ -283,8 +283,8 @@ void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<MachineLoopInfo>();
AU.addRequired<AAResultsWrapperPass>();
AU.addRequired<TargetPassConfig>();
- AU.addRequired<SlotIndexes>();
- AU.addPreserved<SlotIndexes>();
+ AU.addRequired<SlotIndexesWrapperPass>();
+ AU.addPreserved<SlotIndexesWrapperPass>();
AU.addRequired<LiveIntervals>();
AU.addPreserved<LiveIntervals>();
MachineFunctionPass::getAnalysisUsage(AU);
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 0c8a0f2b24a1e..b9b288bff0b35 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -315,7 +315,7 @@ namespace {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addUsedIfAvailable<LiveStacks>();
AU.addUsedIfAvailable<LiveVariables>();
- AU.addUsedIfAvailable<SlotIndexes>();
+ AU.addUsedIfAvailable<SlotIndexesWrapperPass>();
AU.addUsedIfAvailable<LiveIntervals>();
AU.setPreservesAll();
MachineFunctionPass::getAnalysisUsage(AU);
@@ -433,7 +433,8 @@ unsigned MachineVerifier::verify(const MachineFunction &MF) {
if (!LiveInts)
LiveVars = PASS->getAnalysisIfAvailable<LiveVariables>();
LiveStks = PASS->getAnalysisIfAvailable<LiveStacks>();
- Indexes = PASS->getAnalysisIfAvailable<SlotIndexes>();
+ auto *SIWrapper = PASS->getAnalysisIfAvailable<SlotIndexesWrapperPass>();
+ Indexes = SIWrapper ? &SIWrapper->getSI() : nullptr;
}
verifySlotIndexes();
diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp
index 592972f5c83b2..9c0d291e624f8 100644
--- a/llvm/lib/CodeGen/PHIElimination.cpp
+++ b/llvm/lib/CodeGen/PHIElimination.cpp
@@ -137,7 +137,7 @@ INITIALIZE_PASS_END(PHIElimination, DEBUG_TYPE,
void PHIElimination::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addUsedIfAvailable<LiveVariables>();
AU.addPreserved<LiveVariables>();
- AU.addPreserved<SlotIndexes>();
+ AU.addPreserved<SlotIndexesWrapperPass>();
AU.addPreserved<LiveIntervals>();
AU.addPreserved<MachineDominatorTreeWrapperPass>();
AU.addPreserved<MachineLoopInfo>();
diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp b/llvm/lib/CodeGen/RegAllocBasic.cpp
index f465c63cf1040..74497b489b054 100644
--- a/llvm/lib/CodeGen/RegAllocBasic.cpp
+++ b/llvm/lib/CodeGen/RegAllocBasic.cpp
@@ -130,7 +130,7 @@ char &llvm::RABasicID = RABasic::ID;
INITIALIZE_PASS_BEGIN(RABasic, "regallocbasic", "Basic Register Allocator",
false, false)
INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
-INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
+INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
@@ -179,7 +179,7 @@ void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<AAResultsWrapperPass>();
AU.addRequired<LiveIntervals>();
AU.addPreserved<LiveIntervals>();
- AU.addPreserved<SlotIndexes>();
+ AU.addPreserved<SlotIndexesWrapperPass>();
AU.addRequired<LiveDebugVariables>();
AU.addPreserved<LiveDebugVariables>();
AU.addRequired<LiveStacks>();
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 19c1ee23af858..e1e6361da3468 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -155,7 +155,7 @@ char &llvm::RAGreedyID = RAGreedy::ID;
INITIALIZE_PASS_BEGIN(RAGreedy, "greedy",
"Greedy Register Allocator", false, false)
INITIALIZE_PASS_DEPENDENCY(LiveDebugVariables)
-INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
+INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
INITIALIZE_PASS_DEPENDENCY(RegisterCoalescer)
INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
@@ -207,8 +207,8 @@ void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addPreserved<MachineBlockFrequencyInfo>();
AU.addRequired<LiveIntervals>();
AU.addPreserved<LiveIntervals>();
- AU.addRequired<SlotIndexes>();
- AU.addPreserved<SlotIndexes>();
+ AU.addRequired<SlotIndexesWrapperPass>();
+ AU.addPreserved<SlotIndexesWrapperPass>();
AU.addRequired<LiveDebugVariables>();
AU.addPreserved<LiveDebugVariables>();
AU.addRequired<LiveStacks>();
@@ -2724,7 +2724,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
if (!hasVirtRegAlloc())
return false;
- Indexes = &getAnalysis<SlotIndexes>();
+ Indexes = &getAnalysis<SlotIndexesWrapperPass>().getSI();
// Renumber to get accurate and consistent results from
// SlotIndexes::getApproxInstrDistance.
Indexes->packIndexes();
diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp
index 88ba843067e5a..330ecd2762014 100644
--- a/llvm/lib/CodeGen/RegAllocPBQP.cpp
+++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp
@@ -120,7 +120,7 @@ class RegAllocPBQP : public MachineFunctionPass {
/// Construct a PBQP register allocator.
RegAllocPBQP(char *cPassID = nullptr)
: MachineFunctionPass(ID), customPassID(cPassID) {
- initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
+ initializeSlotIndexesWrapperPassPass(*PassRegistry::getPassRegistry());
initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
initializeLiveStacksPass(*PassRegistry::getPassRegistry());
initializeVirtRegMapPass(*PassRegistry::getPassRegistry());
@@ -544,8 +544,8 @@ void RegAllocPBQP::getAnalysisUsage(AnalysisUsage &au) const {
au.setPreservesCFG();
au.addRequired<AAResultsWrapperPass>();
au.addPreserved<AAResultsWrapperPass>();
- au.addRequired<SlotIndexes>();
- au.addPreserved<SlotIndexes>();
+ au.addRequired<SlotIndexesWrapperPass>();
+ au.addPreserved<SlotIndexesWrapperPass>();
au.addRequired<LiveIntervals>();
au.addPreserved<LiveIntervals>();
//au.addRequiredID(SplitCriticalEdgesID);
diff --git a/llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp b/llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp
index e031019a4c917..0650aaff56ea0 100644
--- a/llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp
+++ b/llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp
@@ -51,13 +51,13 @@ class DefaultPriorityAdvisorAnalysis final
private:
void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.addRequired<SlotIndexes>();
+ AU.addRequired<SlotIndexesWrapperPass>();
RegAllocPriorityAdvisorAnalysis::getAnalysisUsage(AU);
}
std::unique_ptr<RegAllocPriorityAdvisor>
getAdvisor(const MachineFunction &MF, const RAGreedy &RA) override {
return std::make_unique<DefaultPriorityAdvisor>(
- MF, RA, &getAnalysis<SlotIndexes>());
+ MF, RA, &getAnalysis<SlotIndexesWrapperPass>().getSI());
}
bool doInitialization(Module &M) override {
if (NotAsRequested)
diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp
index 9f4f23807d82f..3fb7186ab5498 100644
--- a/llvm/lib/CodeGen/RegisterCoalescer.cpp
+++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp
@@ -407,7 +407,7 @@ char &llvm::RegisterCoalescerID = RegisterCoalescer::ID;
INITIALIZE_PASS_BEGIN(RegisterCoalescer, "register-coalescer",
"Register Coalescer", false, false)
INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
-INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
+INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_END(RegisterCoalescer, "register-coalescer",
@@ -590,7 +590,7 @@ void RegisterCoalescer::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<AAResultsWrapperPass>();
AU.addRequired<LiveIntervals>();
AU.addPreserved<LiveIntervals>();
- AU.addPreserved<SlotIndexes>();
+ AU.addPreserved<SlotIndexesWrapperPass>();
AU.addRequired<MachineLoopInfo>();
AU.addPreserved<MachineLoopInfo>();
AU.addPreservedID(MachineDominatorsID);
diff --git a/llvm/lib/CodeGen/RenameIndependentSubregs.cpp b/llvm/lib/CodeGen/RenameIndependentSubregs.cpp
index e888f290df51...
[truncated]
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paperchalice
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aeubanks
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Jul 8, 2024
- Add `SlotIndexesAnalysis`. - Add `SlotIndexesPrinterPass`. - Use `SlotIndexesWrapperPass` in legacy pass.
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aaryanshukla
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Jul 14, 2024
- Add `SlotIndexesAnalysis`. - Add `SlotIndexesPrinterPass`. - Use `SlotIndexesWrapperPass` in legacy pass.
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SlotIndexesAnalysis.SlotIndexesPrinterPass.SlotIndexesWrapperPassin legacy pass.