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[hmac+prim_sha2,rtl] Add RTL for SHA-2 prim and its instantiation in HMAC (256-bit) #21107

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merged 7 commits into from
Feb 1, 2024

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gdessouky
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This PR cherry-picks a bunch of merged commits from the integrated_dev branch into the master branch to:

  1. add the RTL, and updated core files and lint waivers for the prim_sha2 implementation
  2. and its instantiation in HMAC (only 256-bit at the moment)
  3. update the UNR-generated coverage exclusions to bring coverage back to its earlier numbers for HMAC
  4. minor RTL and styling/linting fixes
  5. remove the redundant SHA-2 files from HMAC now that it instantiates the primitive
  6. fix minor waiver file syntax error

This will update HMAC and prim_sha2 in master to match the state in integrated_dev and allow upcoming commits to extend the digest width to 384/512-bit.

gdessouky and others added 7 commits January 30, 2024 11:24
This adds the RTL implementation for the merged SHA-2 prim that can be
configured at compile-time as either multi-mode or 256-bit.
The RTL includes the 32-bit word input wrapper prim_sha2_32 that
instantiates the prim_sha2. This also fixes many coding style issues
that were in the original HMAC IP RTL, and updates the relevant
prim core files. This also updates the lint waivers and RTL fixes,
to pass AscentLint linting.

Signed-off-by: Ghada Dessouky <gdessouky@google.com>
This updates the HMAC RTL to use the SHA-2 256 prim
instantiation as well as the core file. This also
adds fixes the HMAC RTL and updates the linting waiver
to pass AscentLint.

Signed-off-by: Ghada Dessouky <gdessouky@google.com>
This updates the list of coverage exclusions after running
UNR analysis for HMAC when it instantiates the SHA-2 primitive.

Signed-off-by: Ghada Dessouky <gdessouky@google.com>
This adds the synthesis configuration files and modifies
the core to support test synthesis for area estimates in kGE.

Signed-off-by: Ghada Dessouky <gdessouky@google.com>
This makes minor styling fixes and RTL changes to fix
2 AscentLint warnings and avoid waivers for them.

Signed-off-by: Ghada Dessouky <gdessouky@google.com>
The SHA2 moved to a prim that is already instantiated
in the HMAC core

Signed-off-by: Robert Schilling <rschilling@rivosinc.com>
Signed-off-by: Robert Schilling <rschilling@rivosinc.com>
@gdessouky gdessouky requested a review from a team as a code owner January 30, 2024 11:11
@gdessouky gdessouky requested review from matutem, andreaskurth, moidx and msfschaffner and removed request for a team and matutem January 30, 2024 11:11
@gdessouky
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Results look good after running the nightly regression locally:

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 4.160s 1.742ms 50 50 100.00 %
V1 csr_hw_reset hmac_csr_hw_reset 0.560s 35.847us 5 5 100.00 %
V1 csr_rw hmac_csr_rw 0.610s 96.341us 20 20 100.00 %
V1 csr_bit_bash hmac_csr_bit_bash 8.170s 2.588ms 5 5 100.00 %
V1 csr_aliasing hmac_csr_aliasing 2.400s 163.370us 5 5 100.00 %
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 10.155m 213.950ms 20 20 100.00 %
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 0.610s 96.341us 20 20 100.00 %
hmac_csr_aliasing 2.400s 163.370us 5 5 100.00 %
V1 TOTAL 105 105 100.00 %
V2 long_msg hmac_long_msg 1.829m 24.737ms 50 50 100.00 %
V2 back_pressure hmac_back_pressure 56.770s 3.813ms 50 50 100.00 %
V2 test_vectors hmac_test_sha_vectors 7.910m 47.861ms 48 50 96.00 %
hmac_test_hmac_vectors 1.080s 288.771us 50 50 100.00 %
V2 burst_wr hmac_burst_wr 59.740s 1.512ms 50 50 100.00 %
V2 datapath_stress hmac_datapath_stress 2.247m 8.285ms 50 50 100.00 %
V2 error hmac_error 3.150m 124.743ms 50 50 100.00 %
V2 wipe_secret hmac_wipe_secret 1.257m 19.540ms 50 50 100.00 %
V2 stress_all hmac_stress_all 35.640m 292.592ms 50 50 100.00 %
V2 alert_test hmac_alert_test 0.500s 15.131us 50 50 100.00 %
V2 intr_test hmac_intr_test 0.510s 35.720us 50 50 100.00 %
V2 tl_d_oob_addr_access hmac_tl_errors 3.350s 69.484us 20 20 100.00 %
V2 tl_d_illegal_access hmac_tl_errors 3.350s 69.484us 20 20 100.00 %
V2 tl_d_outstanding_access hmac_csr_hw_reset 0.560s 35.847us 5 5 100.00 %
hmac_csr_rw 0.610s 96.341us 20 20 100.00 %
hmac_csr_aliasing 2.400s 163.370us 5 5 100.00 %
hmac_same_csr_outstanding 1.250s 78.424us 20 20 100.00 %
V2 tl_d_partial_access hmac_csr_hw_reset 0.560s 35.847us 5 5 100.00 %
hmac_csr_rw 0.610s 96.341us 20 20 100.00 %
hmac_csr_aliasing 2.400s 163.370us 5 5 100.00 %
hmac_same_csr_outstanding 1.250s 78.424us 20 20 100.00 %
V2 TOTAL 588 590 99.66 %
V2S tl_intg_err hmac_sec_cm 0.840s 157.175us 5 5 100.00 %
hmac_tl_intg_err 2.220s 773.032us 20 20 100.00 %
V2S sec_cm_bus_integrity hmac_tl_intg_err 2.220s 773.032us 20 20 100.00 %
V2S TOTAL 25 25 100.00 %
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 4.160s 1.742ms 50 50 100.00 %
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.069h 151.730ms 192 200 96.00 %
V3 TOTAL 192 200 96.00 %
TOTAL 910 920 98.91 %

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.42 % 99.55 % 98.55 % 100.00 % 100.00 % 98.47 % 99.49 % 99.86 %

@msfschaffner msfschaffner requested a review from vogelpi February 1, 2024 01:29
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LGTM - @andreaskurth or @vogelpi please merge if it looks good to you.

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Nice, LGTM. Thanks @gdessouky!

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4 participants