[otbn] Fix interpretation of lc_rma_req signal values

[vogelpi]

Now that #21267 changes LC_CTRL to receive multiple RMA ack signals in parallel and the RMA req/ack signals for Flash and OTBN are no longer daisy-chained in Earlgrey, this change can and must be done because:

• A glitch into the RMA req/ack signals can no longer bypass Flash wiping before RMA entry. I.e., the checking of the RMA req signal in OTBN can thus be fully aligned with the LC_CTRL spec.
• The RMA req signal seen by OTBN is no coming from a different clock domain and OTBN will observe staggered transitions. By aligning the signal interpretation in OTBN with the LC_CTRL spec, it can actually handle that.

Note that this is a cherry pick of 388567f from the intergrated_dev branch:

According to the lc_ctrl spec, all values of non-escalation lc signals other than ON must be intrepreted as OFF. Also, no detection of invalid values should be performed as these signals might experience staggered transitions due to CDCs naturally leading to invalid values.

This commit changes the design accordingly to match this spec.

This resolves #19050.

[vogelpi]

@rswarbrick this might cause similar failures on master as you observed in integrated_dev recently and reported in #20835 .

[msfschaffner]

LGTM!