[sram_ctrl] Add readback feature #23212
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When enabled with the SRAM_CTRL.READBACK CSR, the SRAM readback mode checks each read and write to the SRAM. On a read, the readback mode issues a second read to the same address to check, whether the correct data was fetched from memory. On a write, the readback mode issues a read to check, whether the data was actually written into the memory. To avoid that the holding register is read, the readback is delayed by one cycle. On a mismatch, a fatal error is triggered and the STATUS.READBACK_ERROR register is set. To avoid RTL changes as much as possible, the readback mode is implemented in the tlul_sram_byte module. In this module, after the initial read or write was executed, the bus interface to the host is stalled and the readback is performed. Due to the bus stalling, a performance impact is expected. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org> Co-authored-by: Greg Chadwick <gac@lowrisc.org>
vogelpi
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The one failing CI check (CW310 Test ROM) seems to be unrelated to this PR; all other checks passed --> merging |
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This commit updates the RAM ports inside ibex_top to reflect recent changes introduced with lowRISC/opentitan#23212 (SRAM readback mode). Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
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This commit adds the DIF functions for the readback mode (c.f. lowRISC#23212)and a basic test. Closes lowRISC#23365 Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
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This commit adds the DIF functions for the readback mode (c.f. lowRISC#23212) and a basic test. Closes lowRISC#23365 Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
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This commit adds the DIF functions for the readback mode (c.f. lowRISC#23212) and a basic test. Closes lowRISC#23365 Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
This was referenced Jun 3, 2024
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This commit updates the RAM ports inside ibex_top to reflect recent changes introduced with lowRISC/opentitan#23212 (SRAM readback mode). Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
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This commit updates the RAM ports inside ibex_top to reflect recent changes introduced with lowRISC/opentitan#23212 (SRAM readback mode). Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
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With the introduction of the SRAM readback mode (c.f., lowRISC#23212) memory requests can be delayed. The sram_ctrl_passthru_mem_tl_intg_err failed occasionally because the integrity alert was expected to arrive without any delay. This commit increases the max_delay parameter for the expected alert to take the readback mode delay into account. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
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With the introduction of the SRAM readback mode (c.f., lowRISC#23212) memory requests can be delayed. The SRAM DV tests are adapted such that the readback feature can be disabled or enabled anytime during a test. The sram_ctrl_passthru_mem_tl_intg_err failed occasionally because the integrity alert was expected to arrive without any delay. This commit increases the max_delay parameter for the expected alert to take the readback mode delay as well as a potential enabling or disabling of the feature into account. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
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With the introduction of the SRAM readback mode (c.f., #23212) memory requests can be delayed. The SRAM DV tests are adapted such that the readback feature can be disabled or enabled anytime during a test. The sram_ctrl_passthru_mem_tl_intg_err failed occasionally because the integrity alert was expected to arrive without any delay. This commit increases the max_delay parameter for the expected alert to take the readback mode delay as well as a potential enabling or disabling of the feature into account. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
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With the introduction of the SRAM readback mode (c.f., lowRISC#23212) memory requests can be delayed. The SRAM DV tests are adapted such that the readback feature can be disabled or enabled anytime during a test. The sram_ctrl_passthru_mem_tl_intg_err failed occasionally because the integrity alert was expected to arrive without any delay. This commit increases the max_delay parameter for the expected alert to take the readback mode delay as well as a potential enabling or disabling of the feature into account. Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
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When enabled with the SRAM_CTRL.READBACK CSR, the SRAM readback mode checks each read and write to the SRAM.
On a read, the readback mode issues a second read to the same address to check, whether the correct data was fetched from memory. On a write, the readback mode issues a read to check, whether the data was actually written into the memory. To avoid that the holding register is read, the readback is delayed by one cycle.
On a mismatch, a fatal error is triggered and the STATUS.READBACK_ERROR register is set.
To avoid RTL changes as much as possible, the readback mode is implemented in the tlul_sram_byte module. In this module, after the initial read or write was executed, the bus interface to the host is stalled and the readback is performed. Due to the bus stalling, a performance impact is expected.