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@RoaLogic Roa Logic BV

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    31 repositories

    • virtualdevboard

      Public
      Graphical Virtual SoC Development Board Builder using Verilator
      C++
      •
      BSD 3-Clause "New" or "Revised" License
      •0•0•0•0•Updated Mar 6, 2025Mar 6, 2025

    • Hamming-ECC

      Public
      Hamming ECC Encoder and Decoder to protect memories
      SystemVerilog
      •
      Other
      •23•30•0•2•Updated Jan 28, 2025Jan 28, 2025

    • Verilator-simulation

      Public
      Collection of C++ classes to create Verilator Testbenches
      C++
      •
      GNU General Public License v3.0
      •0•2•0•0•Updated Nov 2, 2024Nov 2, 2024

    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      •
      ISC License
      •918•0•0•1•Updated Sep 24, 2024Sep 24, 2024

    • RV12

      Public
      RISC-V CPU Core
      cpurisc-v32-bit64bit
      SystemVerilog
      •
      Other
      •54•317•5•0•Updated Jun 8, 2024Jun 8, 2024

    • rv_soc

      Public
      Roa Logic RISC-V SoC
      SystemVerilog
      •2•1•0•0•Updated May 21, 2024May 21, 2024

    • ahb3lite_sdram_ctrl

      Public
      AHB3 Lite SDRAM Controller
      SystemVerilog
      •
      Other
      •1•1•0•0•Updated May 21, 2024May 21, 2024

    • apb4_uart16550

      Public
      16550 UART with APB4 Interface
      SystemVerilog
      •
      BSD 2-Clause "Simplified" License
      •2•4•0•0•Updated May 14, 2024May 14, 2024

    • ahb3lite_interconnect

      Public
      AHB3-Lite Interconnect
      switchinterconnectambaahb3-lite
      SystemVerilog
      •
      Other
      •27•85•1•0•Updated May 10, 2024May 10, 2024

    • adv_dbg_if

      Public
      Universal Advanced JTAG Debug Interface
      SystemVerilog
      •11•17•0•0•Updated May 10, 2024May 10, 2024

    • apb_error

      Public
      APB module that always generates an error response
      SystemVerilog
      •
      BSD 2-Clause "Simplified" License
      •1•1•0•0•Updated May 10, 2024May 10, 2024

    • ahb3lite_error

      Public
      AHB module that always generates an error response
      SystemVerilog
      •
      BSD 2-Clause "Simplified" License
      •1•1•0•0•Updated May 10, 2024May 10, 2024

    • apb4_gpio

      Public
      General Purpose IO with APB4 interface
      gpioambaapb
      SystemVerilog
      •
      Other
      •9•12•0•0•Updated May 10, 2024May 10, 2024

    • ahb3lite_memory

      Public
      Multi-Technology RAM with AHB3Lite interface
      ambaahb3-liteahb3lite-memory
      SystemVerilog
      •
      Other
      •15•21•0•0•Updated May 10, 2024May 10, 2024

    • apb4_mux

      Public
      APB4 Multiplexor
      apb
      SystemVerilog
      •
      Other
      •5•13•0•0•Updated May 10, 2024May 10, 2024

    • ahb3lite_apb_bridge

      Public
      Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
      ambaahb3-liteapbapb-bridge
      SystemVerilog
      •
      Other
      •20•42•1•1•Updated May 10, 2024May 10, 2024

    • ahb3lite_timer

      Public
      RISC-V compliant Timer IP
      timerrisc-vahb3-lite
      SystemVerilog
      •
      Other
      •7•13•0•0•Updated May 10, 2024May 10, 2024

    • plic

      Public
      Platform Level Interrupt Controller
      SystemVerilog
      •
      Other
      •15•36•5•0•Updated May 10, 2024May 10, 2024

    • universal_jtag_tap

      Public
      Universal JTAG TAP Controller
      SystemVerilog
      •5•9•0•0•Updated May 9, 2024May 9, 2024

    • ahb3lite_pkg

      Public
      Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
      SystemVerilog
      •10•17•0•0•Updated Apr 27, 2024Apr 27, 2024

    • memory

      Public
      Generic memory implementations
      SystemVerilog
      •
      Other
      •12•10•1•0•Updated Feb 6, 2024Feb 6, 2024

    • rltheme

      Public
      Roa Logic Theme for GitHub Pages
      TeX
      •0•0•0•0•Updated Dec 29, 2023Dec 29, 2023

    • 8b10b

      Public
      8b10b encoder/decoder
      Scilab
      •
      BSD 2-Clause "Simplified" License
      •1•0•0•0•Updated Nov 25, 2023Nov 25, 2023

    • rv_c_demos

      Public
      C demo code to use with the rv_soc
      C
      •
      MIT License
      •0•0•0•0•Updated Nov 6, 2023Nov 6, 2023

    • OpenOCD

      Public
      OpenOCD clone for porting RoaLogic Debuggers
      C
      •
      GNU General Public License v2.0
      •2•0•0•0•Updated Dec 1, 2021Dec 1, 2021

    • roalogic.github.io

      Public
      Roa Logic GitHub Pages Site (Top Level)
      asicfpgariscvipapbroalogicahb
      SCSS
      •3•4•0•0•Updated Nov 20, 2020Nov 20, 2020

    • vi_systemverilog_syntax

      Public
      VIM Syntax file for SystemVerilog
      syntax-highlightingvimsystemverilogvim-syntaxvi-systemverilog-syntax
      Vim Script
      •2•5•0•0•Updated Aug 16, 2019Aug 16, 2019

    • vga_lcd

      Public
      VGA LCD Core (OpenCores)
      Verilog
      •
      BSD 2-Clause "Simplified" License
      •6•13•1•0•Updated May 22, 2018May 22, 2018

    • riscv-isa-manual

      Public
      RISC-V Instruction Set Manual
      TeX
      •
      Creative Commons Attribution 4.0 International
      •685•1•0•0•Updated Sep 27, 2017Sep 27, 2017

    • riscv_gnu_eclipse

      Public
      Eclipse Plugin for RISC-V GNU Toolchain
      risc-vtoolchaineclipseriscv-gnu-eclipse
      Java
      •4•4•0•0•Updated Jun 27, 2017Jun 27, 2017