V 11 (1986)

The V-11 (code name Scorpio) was DEC's first VAX microprocessor design, although the second to ship.  Bill Johnson was the project manager; Ed Burdick was lead engineer on the IE chip, Bill Grundmann on the M chip; Dick Sites led the architecture and microcode teams.

The Scorpio program aimed at launching DEC into the VLSI design era. In addition V-11 itself, Scorpio encompassed a new CAD suite (CHAS) and DEC's first in-house process development effort (and the industry's first double-metal process), ZMOS. V-11 implemented a full VAX, with a robust memory and console system, suitable for mid-range systems as well as embedded systems.

V-11 consisted of four chips, one of which could be replicated: the ROM/RAM chip, the IE (instruction execution) chip, the M (memory management) chip, and the F (floating point chip). Five copies of the ROM/RAM were required to implement the full VAV instruction set. V-11 initially ran at 5Mhz, with a high-speed bin point at 6.25Mhz.

Name	Number	Size	Transistors	Comments
MicroVAX CPU	DC333	353x358	125,000 sites	The MicroVAX CPU is a high performance, single chip 32b microprocessor that implements a compatible subset of the VAX architecture. Key features include: High performance 32b internal and external data path Pipelined architecture Instruction prefetch Subset VAX architecture Sixteen 32b general purpose registers 175 instructions 21 addressing modes 6 data types VAX memory management 4GB virtual address space 64MB physical address space Demand paging Memory protection Four privilege modes Vectored multi-level interrupts (15 software, 7 hardware) Industry compatible external interface Single +5V supply Power: 2.5W.
MicroVAX FPU	DC337	339x272	34,000	The MicroVAX FPU is a high performance, single chip floating point processor for the MicroVAX CPU. Its key features are: High performance Implements all floating point operations Accelerates integer multiply and divide f_, d_, and g_floating point format support Full VAX floating point instruction set, including ACBf, EMODf, POLYf Arithmetic error checking and reporting Single +5V supply Power: 2.5W.

V-11 shipped in early 1986 in the VAX 8200 and 8300 mid-range systems. By that time, MicroVAX II had been out for more than six months and had captured the attention of the company and the customer base. A mid-life kicker, the VAX 8250 and 8350, based on binned parts, shipped in 1987.

Personal Narrative

V-11 attempted to do "six impossible things before breakfast" -- new methodology, new CAD tools, new architecture, new process, new design team, new organization -- and it paid the price for being a pioneer: a long development schedule filled with mishaps. MicroVAX, by starting later and dropping much of the complexity of the VAX architecture, reaped the benefits of V-11's (bitter) experiences, pillaged its microarchitecture and design objects, and shipped first. Yet V-11 fulfilled the intentions of its creators in revolutionizing DEC's approach to chip design. Before V-11, DEC used partners for process design, did its chip design work on paper, and had a small design group capable of one design at a time. After V-11, DEC did its own process development, did its chip design work entirely via CAD tools, and had a design group capable of building multiple chips in parallel.

Once MicroVAX was on the drawing boards, the V-11 management team made a determined effort to simplify the design and get it out the door. V-11's unique F-chip was dropped in favor of a derivative of the J-11 FPA. Features were stripped from the IE chip to get the size and power down. Even though MicroVAX could be considered an internal competitor, the entire V-11 team was extraordinarily gracious in providing support to the MicroVAX team.

I became the manager of microprocessor development in October, 1984, and thus supervised the last 15 months of V-11. My only real contribution was to utilize spare space in the control store patch RAM to recode CALLS and CALLG for higher performance, based on studies done for CVAX.

V11 was presented at the 1984 International Solid State Circuits Conference.