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riscv-isa-sim
riscv-isa-sim PublicForked from riscv-software-src/riscv-isa-sim
RISC-V Functional ISA Simulator
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riscv-tools
riscv-tools PublicForked from riscv-software-src/riscv-tools
RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)
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21 contributions in the last year
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Contribution activity
April 2025
Opened 1 pull request in 1 repository
lowRISC/opentitan
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[topgen,alert_handler] Explicitly specify alert handler connections
This contribution was made on Apr 4
Reviewed 1 pull request in 1 repository
lowRISC/opentitan
1 pull request
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[topgen] Support for outgoing interrupts
This contribution was made on Apr 7
Created an issue in lowRISC/opentitan that received 1 comment
[ipgen] Unclear when to use templatization or SystemVerilog parameters
We have two methods for parameterizing hardware: the usual SystemVerilog parameter system, as well as Mako templates rendered by ipgen. As I unders…
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Opened 1 other issue in 1 repository
lowRISC/opentitan
1
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[otp_ctrl] Verilator linting PartInvDefault breaks on overly long vector
This contribution was made on Apr 4