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1. System_Verilog_Assertion_to_RTL_Synthesizer System_Verilog_Assertion_to_RTL_Synthesizer Public

   A synthesizer capable of transforming SVA properties into synthesizable hardware modules in Verilog register-transfer level (RTL).

   Python 2

2. Physical-Design-Aware-Power-Dataset Physical-Design-Aware-Power-Dataset Public

3. shamstarekargho/Hardware-Vulnerability-Dataset shamstarekargho/Hardware-Vulnerability-Dataset Public

   This repository contains 4000 vulnerable hardware designs. Currently this is in Jsonl format for directly using it for fine-tuning LLMs. This is open to everyone for use. Thanks!

   11

4. SecRT-LLM SecRT-LLM Public

   Hardware Vulnerability Detection Framework Using Large Language Model

   Python 1

5. HW_Security_Threat_Knowledge_Extraction HW_Security_Threat_Knowledge_Extraction Public

   HW Security Threat Knowledge Extraction from Papers Through RAG

   Python

6. LLM-for-SoC-Security-Case-Studies LLM-for-SoC-Security-Case-Studies Public

   1