An almost empty chisel project (and adder) as a starting point for hardware design.
To generate Verilog code for the adder execute:
makeRun the tests with:
make testCleanup the repository with:
make clean
generated from schoeberl/chisel-empty
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Tappu is a Tape based CPU implemented in Chisel
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tobias1012/Tappu
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Tappu is a Tape based CPU implemented in Chisel
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