AMBA AXI VIP

Network on Chip Implementation written in SytemVerilog

An AXI4 crossbar implementation in SystemVerilog

AHB3-Lite Interconnect

Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

Verification IP for AMBA APB Protocol

Multi-Technology RAM with AHB3Lite interface

Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation including a final report and project progression presentation.

APB master and slave developed in RTL.

General Purpose IO with APB4 interface

Multi-port BRAM IP for ASIC and FPGA

A presentation about Advanced Microcontroller Bus Architecture

Knowledge hub for digital interfaces