This repository contains source code for past labs and projects involving FPGA and Verilog based designs

Digital System Design Lab Codes using Verilog

Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur

Verilog code and testbench for 4-bit full adder

This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.

An 8-bit calculator that can multiply, add and subtract. Created and simulated in Quartus Prime and physically implemented in DEC-SOC1 FPGA.

A repository for some modules I made while learning Verilog

CSE-2112 Digital Syatem Design LAb

Sumador de dos números de dos dígitos cada uno codificados en ASCII estándar en 7 bits. Restricción: realizar la suma en binario natural.

basic implementation of logic structures using verilog (revising github)

Verilog code to implement 8 bit full adder and demonstration of the result on FPGA board.

Gate-level implementation of a full-adder using Verilog, complete with a testbench, truth table validation, and waveform analysis for beginners in digital logic design.