icarus-verilog

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An abstraction library for interfacing EDA tools

SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

python flow simulator tdd simulation foss verilog testcase tdd-utilities mit-license systemverilog icarus-verilog gtkwave verification-methodologies vcd verilator surfer svut

Example of how to get started with olofk/fusesoc.

vivado icestorm icarus-verilog yosys fusesoc tinyfpga-bx nexys-a7 nextpnr-ice40

Example of Python and PyTest powered workflow for a HDL simulation

python asic fpga pytest rtl verilog icarus-verilog hdl modelsim system-verilog vivado-simulator

🪀 Tool to play with HDL (inspired by EdaPlayground)

eda verilog vcs systemverilog icarus-verilog hdl modelsim verilator

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