A processor cache simulator for the MIPS architecture

💻 MIPS Pipeline Processor simulator

An imaginary 16-bit CPU architecture with custom assembly language and instructions

Python simulator of Tomasulo algorithm

Continuation of a functional Tomasulo out-of-order processor, with a cache prefetcher and replacement policy. Implements most of the RV32I ISA.

A Python model for a RISC-V Single Cycle Processor and simple Assembler

Flote is a HDL and Python framework for simulation. Designed to be friendly, simple, and productive. Easy to use and learn.

RISC-V cores based on Bluespec's Piccolo and Flute

Superscalar 8 bit processor made in logisim and corresponding assembly language to bit code compiler.

Simple MicroProcessor Architecture - Tiny 8 bit CPU

Custom processor implemented in logisim-evolution

SEA-IV is a simple assembler for the MOOn-IV architecture. It is written in Python 3 and is a command-line tool.

Implementation of the processor model

Python script to fill your computer memory with processor bits word size

General-purpose processor with a 16-bit address & 32-bit data bus

The project consists of designing a processor in LogiSim that implements the S-MIPSv2 (Simplified-MIPS Version 2) instruction set architecture.