A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
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Dec 2, 2019 - Verilog
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riscv32
Here are 42 public repositories matching this topic...
SCARV: a side-channel hardened RISC-V platform
open-source cryptography cpu crypto riscv verilog research-project mit-license ise formal-verification yosys instruction-set-architecture verilator riscv32 xcrypto
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Jan 11, 2023 - Verilog
Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.
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Oct 29, 2024 - Verilog
Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.
cpu verilog risc hdl pipeline-processor verilog-hdl risc-v rv32i verilog-snippets pipeline-cpu risc-processor riscv32 riscv-simulator rv32imc verilog-code riscv32im
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May 29, 2020 - Verilog
Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-mapped L1 Data Cache, and a 4-way set-associative L2 Victim Cache with a fully-associative 8-entry Victim Buffer. Also has a tournament branch predictor (global and local predictors) and a set-associative BTB.
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Dec 23, 2022 - Verilog
A RISC-V Single Cycle Processor which is done in verilog.
module verilog vivado computer-architecture risc-v 32-bit hardware-description-language riscv32 risc-architecture-processor single-cycle-processor testbench-generator-verilog
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Jul 20, 2020 - Verilog
Risc-V 32i processor written in the Verilog HDL
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Nov 27, 2022 - Verilog
Processador RISC-V de ciclo único com implementação RV32I construído em alguns dias de folga.
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Mar 22, 2024 - Verilog
32 bit Risc-5 mimari işlemci tasarımı
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Nov 21, 2022 - Verilog
The project description of this project was the major project in the Computer Architecture course. It's a RISC-V processor and tested on Nexys A7 kit.
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Feb 9, 2021 - Verilog
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