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dpretet / async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

Updated Apr 30, 2024
Verilog

abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor

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I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be …

asic fpga vhdl rtl verilog synthesis fft soc asic-verification asic-design

Updated Dec 3, 2023
Verilog

JeffDeCola / my-verilog-examples

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A place to keep my synthesizable verilog examples.

simulator asic fpga hardware waveform verilog xilinx synthesis vivado systemverilog gtkwave hdl iverilog hardware-description-language verilog-simulator asic-design synthesize hardware-architecture

Updated Mar 12, 2025
Verilog

basemhesham / Design-and-ASIC-Implementation-of-UART

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This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II

asic dft verilog synthesis uart fm pnr

Updated Apr 29, 2024
Verilog

fayizferosh / yosys-tcl-ui-report

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5 Day TCL begginer to advanced training workshop by VSD

linux bash open-source csv workshop tcl synthesis yosys shell-scripting vlsi-physical-design hardware-description-language static-timing-analysis tcl-programming tcl-extensions tcl-procedures opentimer eda-tools

Updated Oct 18, 2023
Verilog

addisonElliott / SCIC

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Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.

asic cpu digital simulation tcl rtl verilog synthesis icarus-verilog gate cadence

Updated Nov 29, 2018
Verilog

mostafa-elgendy22 / PrUcess

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PrUcess is a low-power multi-clock configurable digital processing system that executes commands (unsigned arithmetic operations, logical operations, register file read & write operations) which are received from an external source through UART receiver module and it transmits the commands' results through the UART transmitter module.

dft verilog synchronizer synthesis formal-verification uart-protocol physical-design asic-design

Updated Apr 29, 2023
Verilog

abdelazeem201 / ASIC-Implementation-UART

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This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from sys…

asic fpga vhdl eda rtl verilog synthesis uart soc pnr

Updated Mar 30, 2022
Verilog

Saadia-Hassan / 8x8Multiplier-Using-Vedic-Mathematics

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An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.

simulation synthesis verilog-hdl xilinx-ise multiplier adders vedic-mathematics

Updated Jul 27, 2020
Verilog

tatan432 / AES_ENCODER

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RTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.

digital rtl aes-128 synthesis aes-encryption digital-design verilog-project encription synopsys-vcs synopsys-dc ee4415

Updated Dec 11, 2020
Verilog

gabrielganzer / DLX-Microprocessor

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Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.

optimization polito microprocessor synthesis synopsys dlx cadence digital-design physical-design dlx-microprocessor

Updated Jun 9, 2021
Verilog

Siddharth13s / RISC-V_Synthesis_and_Physical_Design

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Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo

routing verilog synthesis cts placement tcl-scripts physical-design floorplanning synopsys-dc synopsys-iccii powerplanning

Updated Jul 31, 2024
Verilog

Abdelrahman1810 / SPI_Slave_with_Single_Port_RAM

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This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

rtl verilog finite-state-machine synthesis vivado systemverilog questasim testbench rtl-design

Updated Aug 4, 2024
Verilog

gabrielganzer / VHDL-DesignSynthesis

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Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.