This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools

FPGA Tetris written in Verilog

The Repository contains the code of various Digital Circuits

A Verilog based Fractal Set Generator for the Xilinx Artix 7

An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.

Digital System Design Project - Spring 2020

A single cycle CPU running MIPS instructions on Xilinx FPGA

16-bit MIPS processor implemented in Verilog (as a part of Computer Organisation course)

RISC based 8-bits five stage pipelined processor, operating at 585 MHz clock frequency with 19 I/O pins and 28 instructions having 5 Addressing formats. Tested on Xilinx Artix-7 FPGA.

A multiple cycle CPU running MIPS instructions on Xilinx FPGA

FPGA Messbauer hardware (generator, emulation of signal from gamma-source registered and amplified

Microgramming technology applied to my multiple cycle CPU

🖼✏️ Verilog-based Image Segmentation

To implement the elevator controller, we used Verilog as HDL. The focus of our project was the implementation and verification of a controller for a basic elevator functionality. We also proposed a methodology that utilizes the SCAN algorithm to enhance the efficiency and reliability of the controller.

Design of a system bus architecture - Team Project @ ENTC UoM

Uart=Stands for Universal Asynchronous Reception and Transmission (UART).A simple serial communication protocol that allows the host communicates with the auxiliary device.UART supports bi-directional, asynchronous and serial data transmission.It has two data lines, one to transmit (TX) and another to receive (RX) which is used to communicate th…

UART implementation using Verilog HDL

AUT Logic Design Lab